SLVAFK3 june 2023 AM2431 , AM2432 , AM2434 , TPS65219
There are three different orderable part number (OPN) variants of the TPS65219 PMIC that come factory programmed to power the AM243x. Selecting the right OPN will be based on the application use case and design requirements. Table 3-1 compares the NVM configurations from the output voltages on each rail to the configuration of the digital pins as well as the package options. For additional detailed information, please refer to the device data sheet and technical reference manual (TRM) available at TI.com.
Note, the AM243x comes in both the ALX Package and the ALV package. The AM243x (ALX Package) body size is 11 mm × 11 mm, and does not support LPDDR4 or DDR4 memory. The AM243x (ALV Package) body size is 17.2 mm × 17.2 mm, which has a benefit of pin-to-pin compatibility with the AM64x. The three TPS65219 orderables detailed in this application note are optimized for the AM243x (ALV Package).
If using the AM243x (ALX Package), LP87334DRHDR PMIC is recommended as the optimized power solution for the AM243x core rails. Please refer to Section 5.3 of Using LP8733xx and TPS65218xx PMICs to Power AM64xand AM243x Sitara Processors, application note for more details on this power solution. If the AM243x (ALX Package) is being used in a system with several peripherals, we recommend user-programming TPS65219 to power both the AM243x core rails and additional peripherals.
| TPS6521904 | TPS6521907 | TPS6521908 | ||
|---|---|---|---|---|
| Use Case | Vsys | 3.3 V | 5 V | 3.3 V |
| External Memory Support | DDR4 | DDR4 | LPDDR4 | |
| BUCK1 | Vout | 0.85 V | 0.85 V | 0.85 V |
| Bandwidth | High bandwidth | High bandwidth | High bandwidth | |
| BUCK2 | Vout | 1.8 V | 3.3 V | 1.8 V |
| Bandwidth | High bandwidth | High bandwidth | High bandwidth | |
| BUCK3 | Vout | 1.2 V | 1.2 V | 1.1 V |
| Bandwidth | High bandwidth | High bandwidth | High bandwidth | |
| LDO1 | Vout | 3.3 V (Bypass) | 3.3 V (Bypass) | 3.3 V (Bypass) |
| LDO2 | Vout | 1.8 V (Bypass) | 1.8 V | 1.2 V (Disabled by default) |
| LDO3 | Vout | 1.8 V | 1.8 V | 1.8 V |
| LDO4 | Vout | 2.5 V | 2.5 V | 2.5 V |
| GPIO | GPO1 | Disabled | Enabled | Disabled |
| GPO2 | Enabled | Disabled | Enabled | |
| GPIO | Disabled | Disabled | Disabled | |
| Multi-Device | Disabled | Disabled | Disabled | |
| MODE_RESET | Config | Warm reset | Warm reset | Warm reset |
| MODE_STANDBY | Config | Mode and Standby | Mode and Standby | Mode and Standby |
| VSEL_SD_DDR | Config | SD | SD | SD |
| Polarity | High = VOUT Low = 1.8 V | High = VOUT Low = 1.8 V | High = VOUT Low = 1.8 V | |
| Rail | LDO1 | LDO1 | LDO1 | |
| EN_PB_VSENSE | Config | Push-button | Enable | Enable |
| First Supply detection [1] | FSD config | Enabled | Enabled | Enabled |
| Orderable Part Number | Package size 5 x 5 mm | TPS6521904RHBR | TPS6521907RHBR | TPS6521908RHBR |
| Package size 4 x 4 mm | TPS6521904RSMR | N/A | N/A | |
Technical Reference Manual | TPS6521904 TRM | TPS6521907 TRM | ||
[1] First Supply detection allows power-up as soon as supply voltage is applied, even if EN/PB/VSENSE pin is at OFF_REQ status. FSD can be used in combination with any ON-request configuration, EN, PB or VSENSE. At first power-up the EN/PB/VSENSE pin is treated as if it had a valid ON request.