4 TPS6521904 Powering AM243x

Use case: VSYS=3.3V, DDR4 Memory

Figure 4-1 shows the TPS6521904 variant powering the AM243x on a system with 3.3 V input supply and DDR4 memory.

The 3.3 V coming from the pre-regulator is connected to the main input supply for reference system (VSYS) and to the power input of the buck converters (PVIN_Bx) and LDO1, LDO3, and LDO4 (PVIN_LDO1, PVIN_LDO34). The 3.3 V coming from the pre-regulator can be combined with a power switch to supply the 3.3 V VDDSHVx IO domain. Buck1, Buck2, and LDO3 power the remaining core rails of the AM243x. processor. Buck3 and LDO4 support the required voltages to power the DDR4 memory.

LDO1 and LDO2 are free power resources that can be used for external peripherals, such as 3.3-V rail required for I/Os and an additional 2.5-V rail for the Ethernet PHYs. LDO1, configured as bypass, allows dynamic changes between 3.3 V and 1.8 V. This voltage change on LDO1 can be triggered by I2C or by setting the VSEL_SD pin high (LDO1=3.3 V) or low (LDO1=1.8 V). GPIO and GPO1 are free digital resources that are disabled by default but could be enabled through I2C if needed. GPO2 is pre-programmed to be enabled in the second slot of the power-up sequence with a duration of 6ms. It can be used to enable the external power switch and meet the processor sequence requirements. The switch must be selected with the right electrical spec to ramp and provide a stable output voltage within the 6ms duration of the second slot (before the PMIC starts the next slot in the power-up sequence). TPS6521904 comes pre-programmed, but maintains user-programmable functionality as a NVM device that allows full customization of the output voltages, sequencing, GPIO control, and more to best meet system needs.

Figure 4-2 and Figure 4-3 shows the power-up and power-down sequence programmed on TPS6521904.

Figure 4-1 TPS6521904 Powering AM243x

Figure 4-2 TPS6521904 Power-Up Sequence

Figure 4-3 TPS6521904 Power-Down Sequence