SLVAFQ2 December   2023 TPS65219

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Power Delivery Networks (PDNs)
    1. 2.1 TPS652190C Power Rails Configuration
    2. 2.2 LP87334F Power Rails Configuration
    3. 2.3 Powering i.MX 8M Plus and DDR4
    4. 2.4 Powering i.MX 8M Plus and LDDR4
    5. 2.5 PMICs Digital Configuration
    6. 2.6 Power-Up Sequence
    7. 2.7 Power-Down Sequence
  6. 3Supporting i.MX 8M Plus Low Power Modes
  7. 4PMIC Schematic Example
  8. 5TPS6521905 User-Programmable Version
  9. 6Summary
  10. 7References

Supporting i.MX 8M Plus Low Power Modes

i.MX 8M Plus supports multiple Low Power Modes but not all them affects the PMIC power supplies. This means, some of the low power mode s requires all the PMIC rails to either stay ON or OFF. For example, in RUN Mode and IDLE, all the PMIC rails can stay ON. In OFF Mode, all PMIC rails are turned OFF.

However the SUSPEND and SNVS Modes require specific rails to stay ON while keeping the remaining PMIC rails OFF. These low power modes are optional and not used in some applications. Here are some guidelines to support the low power modes when needed:

Suspend Mode

  • In this mode, all the clocks are off and unnecessary power supplies are off. Buck1 which supplies the VDD_ARM can be turned OFF by software (I2C write to register field BUCK1_EN) or by hardware (only supported when the PMIC MODE/STBY pin is configured as STBY and the Standby state is configured to turn off Buck1).

SNVS Mode

This mode is also called the RTC mode and only the SNVS domain remains on to keep RTC and SNVS operating.

  • Option 1: re-configuring the MODE/STBY pin from MODE only to MODE&STBY and configuring the Standby state to keep LDO3 ON and the remaining rails OFF. This allows to use the MODE/STBY pin to turn-OFF all PMIC rails except LDO3 to support SNVS Mode. In this scenario, the SNVS mode can be triggered from Active state (after the PMIC finishes the default power-up sequence).
  • Option 2: Using an external always ON LDO with power-good that can supply the NVCC_SNVS domain and enable the TPS65219 PMIC. In this use case, LDO3 becomes a free 300mA power resource.
GUID-20231010-SS0I-SQDD-VL0Z-BQTVP03MQDQ8-low.svg Figure 3-1 Powering i.MX 8M Plus and DDR4 - Supports SNVS Low Power Mode
GUID-20231010-SS0I-DVGN-PJBT-HRNSLV8J2B9G-low.svg Figure 3-2 Powering i.MX 8M Plus and LDDR4 - Supports SNVS Low Power Mode