SLVAFQ2 December   2023 TPS65219

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Power Delivery Networks (PDNs)
    1. 2.1 TPS652190C Power Rails Configuration
    2. 2.2 LP87334F Power Rails Configuration
    3. 2.3 Powering i.MX 8M Plus and DDR4
    4. 2.4 Powering i.MX 8M Plus and LDDR4
    5. 2.5 PMICs Digital Configuration
    6. 2.6 Power-Up Sequence
    7. 2.7 Power-Down Sequence
  6. 3Supporting i.MX 8M Plus Low Power Modes
  7. 4PMIC Schematic Example
  8. 5TPS6521905 User-Programmable Version
  9. 6Summary
  10. 7References

5 TPS6521905 User-Programmable Version

Figure 5-1 shows the supply options that are available. If none of the available pre-configured orderable part numbers (OPNs) meet the application requirements or minor changes to the default register settings are needed, a custom NVM is required. For high volume opportunities, TI creates a new orderable part number with custom NVM settings. For low volume opportunities, TI's customers can use the resources listed in Table 5-1 to program the PMIC NVM memory in a production line or through third party programming service. To assist with the PMIC programming, TI facilitates a configuration file with the custom NVM settings that can easily be loaded into the PMIC NVM.

GUID-20230620-SS0I-HBNS-47RG-V69WMSGL77QD-low.svg Figure 5-1 Supply Options
Table 5-1 TPS6521905 Programming Resources
Resource Link
Programming Guide TPS65219 Non-Volatile Memory (NVM) Programming Guide
Graphical User Interface (GUI) TPS65219 graphical user interface
Socketed EVM TPS65219 non-volatile memory (NVM) programming board
TPS6521905 product page User-programmable power management IC (PMIC) with three step-down DC/DC converters and four LDOs