SLVAFQ2 December   2023 TPS65219

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Power Delivery Networks (PDNs)
    1. 2.1 TPS652190C Power Rails Configuration
    2. 2.2 LP87334F Power Rails Configuration
    3. 2.3 Powering i.MX 8M Plus and DDR4
    4. 2.4 Powering i.MX 8M Plus and LDDR4
    5. 2.5 PMICs Digital Configuration
    6. 2.6 Power-Up Sequence
    7. 2.7 Power-Down Sequence
  6. 3Supporting i.MX 8M Plus Low Power Modes
  7. 4PMIC Schematic Example
  8. 5TPS6521905 User-Programmable Version
  9. 6Summary
  10. 7References

4 PMIC Schematic Example

Figure 4-1 shows an example schematic for the minimum required components of the two PMIC solution. This schematic does not include the external discrete that supplies the 3.3V IO. The second PMIC (LP8733) is optional and can be replaced with a discrete Buck when using LPDDR4.

The required output capacitance of the Buck converters in the TPS65219 PMIC is defined based on the configured switching mode and bandwidth. The TPS652190C NVM is configured for quasi-fixed frequency and high bandwidth which requires a minimum of 30uF local output capacitance. 47uF output capacitance per Buck is typically used. Table 4-1 shows the minimum local capacitance and maximum total capacitance for each configuration setting.

Note: The POR_B pin of the i.MX 8M Plus can be driven with an AND gate of the TPS65219_nRSTOUT and the LP8733_PGOOD.
GUID-20231213-SS0I-XR2K-PDRB-7DXHGSHDNGPG-low.svg Figure 4-1 Example PMIC Schematic
Table 4-1 TPS65219 Buck output capacitance
Switching Mode Selection Bandwidth Selection Spec parameter Capacitance
Register Field:

BUCK_FF_ENABLE

 Register fields:

BUCK1_BW_SEL, BUCK2_BW_SEL, BUCK3_BW_SEL

 Min

(local capacitance)

 Max

(local + point of load)
Quasi-fixed frequency

(auto-PFM or forced-PWM)

 Low Bandwidth COUT 10 uF 75 uF
High Bandwidth COUT_HIGH_BW 30 uF 220 uF
Note: For more information about the external component requirements refer to the device data sheet.