SLVAFQ2 December   2023 TPS65219

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Power Delivery Networks (PDNs)
    1. 2.1 TPS652190C Power Rails Configuration
    2. 2.2 LP87334F Power Rails Configuration
    3. 2.3 Powering i.MX 8M Plus and DDR4
    4. 2.4 Powering i.MX 8M Plus and LDDR4
    5. 2.5 PMICs Digital Configuration
    6. 2.6 Power-Up Sequence
    7. 2.7 Power-Down Sequence
  6. 3Supporting i.MX 8M Plus Low Power Modes
  7. 4PMIC Schematic Example
  8. 5TPS6521905 User-Programmable Version
  9. 6Summary
  10. 7References

2.1 TPS652190C Power Rails Configuration

  • The three Buck converters (Buck1, Buck2, Buck3) supports dynamic voltage scaling and are used to supply the VDD_ARM, NVCC_DRAM and NVCC_1.8V (1.8V IO) respectively. Buck2 is configured as 1.2V when using DDR4 and 1.1V when using LPDDR4.
  • LDO1 is configured as bypass to supply the SD card interface. The output voltage of this LDO is set by the VSEL_SD digital pin. An external pull-down resistor on VSEL_SD sets output voltage to 3.3 V initially. After the power-up sequence, the processor can set VSEL_SD high to select 1.8 V level as needed for high-speed card operation per SD specification. This bypass configuration allows control of the LDO1 voltage from 3.3V to 1.8V without the need to establish I2C communication. The bypass configuration on LDO1 requires connecting the input supply pin (PVIN_LDO1) to 3.3V.
  • LDO2 is configured as load-switch and used to supply the uSD card socket. Since this rail is configured as a switch, it requires 3.3 V input supply to output 3.3 V.
  • LDO3 is configured as a standard LDO with 1.8 V output voltage and it is used to supply NVCC_SNVS for applications that do not use the SNVS low power mode. This rail is enabled first in the power-up sequence.
  • LDO4 is a low noise LDO used to supply the 1.8 V analog domain.
Note: For a detailed description of the default TPS652190C register settings, refer to the Technical Reference Manual SLVUCV3