D-CAP2™ and D-CAP3™ converters achieve low ESR ceramic output capacitors through ripple injection circuit. But many designers still prefer to use an electrolytic capacitor or polymer to obtain high capacitance for better ripple and transient performance. This application note discusses the loop stability of the D-CAP2 and D-CAP3 converter using different types of capacitors, especially electrolytic capacitors or polymers. This application note introduces the calculation of the zero and pole with a hybrid output capacitor network based on D-CAP2 and D-CAP3 stage small signal model. The theoretical calculation results are verified by bench loop test. An analysis of the loop stability for the D-CAP2 and D-CAP3 converter with a hybrid output capacitors network is provided. This application note also provides two application design examples based on TPS51386EVM, a 4.5-V to 24-V input, 8-A synchronous buck converter with adaptive on-time D-CAP3 control mode.
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In general, MLCCs have low capacitance and small ESR, and electrolytic capacitors have high capacitance but large ESR. Many designers use MLCCs and electrolytic capacitors in parallel to obtain high capacitance for better ripple and transient performance. However, the electrolytic capacitors have a large ESR, and in DC/DC converter small-signal model, the hybrid output capacitors introduce additional zeros and poles in the loop. And when the ESR of electrolytic capacitors is too large, the zeros and poles are pushed into the bandwidth and have a direct effect on the stability of the loop. This application note calculates the zero and pole of hybrid output capacitor and analyzes the loop stability.