SLVAFQ5 December 2023 TPS51383 , TPS51385 , TPS51386
PRODUCTION DATA
Two different types of capacitors in parallel are common in application designs, so two types of capacitors in parallel are the main focus of discussion here. The simplified equivalent circuit of hybrid output capacitors is shown in Figure 2-1. C1 is the MLCC with small ESR and the C2 is the capacitors with a high capacitance and large ESR, such as electrolytic capacitor or polymer capacitors.
The impedance of a hybrid output capacitor network can be given by Equation 1.
Where, r1 is the ESR of C1; r2 is the ESR of C2
The results show that the hybrid capacitor network introduces an additional zero ωz_C2 and pole ωp_C2 compared to just one type of MLCC capacitor network.
The only difference between the D-CAP2 and D-CAP3 converter is that the D-CAP3 has an error amplifier (EA) to eliminate static errors of output voltage, while the D-CAP2 converter does not have an EA block. Since the EA does not affect the loop analysis with the hybrid capacitor network, the D-CAP3 is used as an example in the next analysis. Figure 2-2 shows a simplified DCAP3 functional block diagram with hybrid capacitor network. The D-CAP2™ Frequency Response Model based on frequency domain analysis of Fixed On-Time with Bottom Detection having Ripple Injection application note, builds on the D-CAP2/3 small-signal model and provides the transfer function from duty to Vout with an MLCC capacitor network. Using a hybrid capacitor network for output in combination with Equation 1 yields the Gdv(s) in Equation 3.
where
C0 is total output capacitance
ω0 is the double pole:
ωz_C1 is the zero generated by C1:
ωz_C2 is the zero generated by C2:
ωp_C2 is the pole generated by the hybrid capacitors network: