SLVAFR4 February   2024 TPS25762-Q1 , TPS25763-Q1 , TPS25772-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Vendor Information File (VIF) Setting
    1. 2.1 Automatic VIF Generation
    2. 2.2 Generate VIF Manually
  6. 3Power Delivery Compliance Test
    1. 3.1 Basic Software for Compliance Test and Results Analysis
  7. 4Power Delivery Source Power Requirements Test
    1. 4.1 SPT.1 Load Test and SPT.2 Capabilities Test
    2. 4.2 SPT.3 Hard Reset Test
    3. 4.3 SPT.5 Over Current Test
    4. 4.4 SPT.6 PPS Voltage Step Test
    5. 4.5 SPT.7 PPS Current Limit Test
  8. 5Analysis of Some Failure Examples
  9. 6Summary
  10. 7References

4.2 SPT.3 Hard Reset Test

GUID-20240104-SS0I-RHXK-LPSH-KRTFNH4M3K7Q-low.gifFigure 4-3 Source VBUS and VCONN Response to Hard Reset

Hard reset signaling indicates a communication failure has occurred and the source stops driving VCONN, removes Rp from the VCONN pin and drives VBUS to vSafe0V. The USB connection resets during a hard reset since the VBUS voltage is less than vSafe5V for an extended period of time. After establishing the vSafe0V voltage condition on VBUS, the source shall wait tSrcRecover before re-applying VCONN and restoring VBUS to vSafe5V. The test also belongs to Power Supply section covering PD CTS 7.1.5.