SLVAFV8 July 2024 TPS25751
Step 1: After applying the VIN_3V3 to the TPS25751, the host can read Interrupt Event for I2C1 Register bit[81] (Offset = 14h) to know if device is read for the patch bundle for the host. The following is the example for the command and the expected result.
[0x20] + ACK (Unique Address/Wr/A)
0x14 + ACK (Register Number/A)
[0x20] + ACK (Unique Address/R/A)
0x0B (Byte Count)
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x02 (MSB)
Step 2: Read Mode (Offset = 3h) to make sure the TPS25751 operating in PTCH mode. The following is the example for the command and the expected result.
[0x20] + ACK (Unique Address/Wr/A)
0x03 + ACK (Register Number/A)
[0x20] + ACK (Unique Address/R/A)
0x04 (Byte Count)
0x50 0x54 0x43 0x48 (‘PTCH’ in 4ASCII characters)
Step 3: Then, prepare to write PBMs by writing DATA1(9h) for each PD controller on the I2Ct bus. DATA1. TargetAddress needs to be the same for all PD controllers. For 4CC command, check if the DATA1 needs to be written corresponding value or just CMD1(8h) for 4CC command. For PBMs 4CC command needs to write DATA1(9h) first and write PBMs 4CC command in CMD1.
[0x20] + ACK (Unique Address/Wr/A)
0x09 + ACK (Register Number/A)
0x06 (Byte Count)
0x80 0x2C 0x00 0x00 0x30 0x32 (Byte1/2/3/4 of bundle size, I2C Target Address, Timeout value)
The bundle size can refer to next section.
| Description | The PBMs Task starts the patch loading sequence. This Task initializes the firmware in preparation for a patch bundle load sequence and indicates what the patch bundle can contain | |||
|---|---|---|---|---|
| INPUT DATAX | Bit |
Name |
Description |
|
| Byte 6: Burst Mode Timeout | ||||
| 7:6 | Reserved | |||
| 5:0 | Timeout value | Timeout value for this task. A non-zero value must be used, always use 0x32 in this field (5 seconds) (LSB of 100ms). | ||
| Byte 5: I2C target for downloading patch. | ||||
| 7 | Reserved | |||
| 6:0 | I2C Target Address | The following target addresses are not valid:
|
||
| Bytes 0-3: Low Region Binary bundle size in of bytes: [ Byte4, Byte3, Byte2, Byte1] | ||||
| 39:32 | Byte4 of bundle size | |||
| 31:24 | Byte3 of bundle size | |||
| 23:16 | Byte2 of bundle size | |||
| 15:8 | Byte1 of bundle size | |||
| OUTPUT DATAX | Bit | Name | Description | |
| 7:0 | PatchStartStatus | Status of the patch start. | ||
| 0x00 | Patch start success | |||
| 0x04 | Invalid bundle size | |||
| 0x05 | Invalid target address | |||
| 0x06 | Invalid Timeout value | |||
| Task Completion | The PBMs Task completes after output has a valid PatchStartStatus. If MODE register (0x03) is equal to APP , then this Task can be rejected. | |||
| Side Effects | When the 'PBMs' is successful, the second target address can be set to the input value. | |||
| Additional Information | The host can only issue a PBMs Task to the I2Ct port of the PD controller. If the host issues PMBs a second time, then the PD controller ignores the DATAX input, restarts the burst-mode timer, and resets the pointer to the beginning of the patch space in RAM. If the MODE register is APP' indicating that the PD controller is in the APP mode, then the host can reject the PBMs Task. | |||
Step 4: After issuing the ‘PBMs’ DATA1, then write CMD1 = ‘PBMs’ on each PD controller on the I2Ct bus.
[0x20] + ACK (Unique Address/Wr/A)
0x08 + ACK (Register Number/A)
0x04 (Byte Count)
0x50 0x42 0x4D 0x73 (‘PBMs’ in 4ASCII characters)
Step 5: Then Read CMD1 register, the expected result is showing as below.
[0x20] + ACK (Unique Address/Wr/A)
0x08 + ACK (Register Number/A)
[0x20] + ACK (Unique Address/R/A)
0x04 (Byte Count)
0x00 0x00 0x00 0x00 (All ‘0x00’ are ok.)
Step6: Then Read DATA1 = 0 (Successfully completed) on each PD controller.
[0x20] + ACK (Unique Address/Wr/A)
0x09 + ACK (Register Number/A)
[0x20] + ACK (Unique Address/R/A)
0x04 (Byte Count)
0x00 0x00 0x00 0x00 (All ‘0x00’ are ok.)
Step7: Write Patch Bundle burst data on the I2Ct bus using the target address specified in DATA1. TargetAddress. Terminate burst data with a Stop bit.
[0x30] + ACK (Unique Address/Wr/A)
0x01 + ACK (Register Number/A)
Write the patch bundle burst data. Next section shows using GUI to generate it.
Step8: Delay at least 500us and Write CMD1=‘PBMc’ on I2Ct bus
[0x20] + ACK (Unique Address/Wr/A)
0x08 + ACK (Register Number/A)
[0x20] + ACK (Unique Address/R/A)
0x04 (Byte Count)
0x50 0x42 0x4D 0x63 (‘PBMc’ in 4ASCII characters)
Step9: Read CMD1 register
[0x20] + ACK (Unique Address/Wr/A)
0x08 + ACK (Register Number/A)
[0x20] + ACK (Unique Address/R/A)
0x04 (Byte Count)
0x00 0x00 0x00 0x00 (All ‘0x00’ are ok.)
Step10: Then Read DATA1 = 0 (Successfully completed) on each PD controller.
[0x20] + ACK (Unique Address/Wr/A)
0x09 + ACK (Register Number/A)
[0x20] + ACK (Unique Address/R/A)
0x04 (Byte Count)
0x00 0x00 0x00 0x00 (All ‘0x00’ are ok.)
Step11: The host can read Interrupt Event for I2C1 Register bit[80] (Offset = 14h) to know if the patch is loaded to the device or not.
Step12: Check the MODE = ‘APP’ on all PD controllers
[0x20] + ACK (Unique Address/Wr/A)
0x03 + ACK (Register Number/A)
[0x20] + ACK (Unique Address/R/A)
0x04 (Byte Count)
0x41 0x50 0x50 0x20 (APP in 4ASCII characters)