SLVK117 October   2022 TPS7H2221-SEP

 

  1.   Single-Event Effects Test Report of the TPS7H2221-SEP Load Switch
  2.   Trademarks
  3. 1 Introduction
  4. 2 Single-Event Effects (SEE)
  5. 3 Device and Test Board Information
  6. 4 Irradiation Facility and Setup
  7. 5 Depth, Range and LETEFF Calculation
  8. 6 Test Setup and Procedures
  9. 7 Destructive Single-Event Effects (DSEE)
    1. 7.1 Single-Event Latch-up (SEL) Results
    2. 7.2 Single-Event Burnout (SEB) and Single-Event Gate Rupture (SEGR) Results
  10. 8 Single-Event Transients (SET) and Single Event Functional Interrupt (SEFI)
    1. 8.1 Single Event Transient (SET)
    2. 8.2 Single Event Functional Interrupt (SEFI)
  11. 9 Event Rate Calculations
  12. 10Summary
  13.   A Appendix: Total Ionizing Dose from SEE Experiments
  14.   B Appendix: References

3 Device and Test Board Information

The TPS7H2221-SEP is packaged in a DCK 6-pin SC70 plastic package as shown in Figure 3-1. The TPS7H2221 EVM was used to evaluate the performance and characteristics of the TPS7H2221-SEP under heavy-ions. Figure 3-2 shows the top view of the board used for the radiation testing. Figure 3-4 shows the board schematics used for the heavy-ion testing campaign.

Note: Because the device is a flip chip, the package was delidded on the bottom to reveal the die face for all heavy-ion testing.
Figure 3-1 Photograph of Delidded TPS7H2221-SEP [Left] and Pinout Diagram [Right]
GUID-20220726-SS0I-XH30-XFRQ-CFK90BPK6FTK-low.jpgFigure 3-2 TPS7H2221-SEP Board Top View.

Because this device is a flip chip a hole was drilled in the board and SEE testing was done "from the back". The ability to see the exposed die through the hole was validated on all EVMs prior to SEE testing. Since the board is dual-site both units were verified and used for testing while under the beam. The boards used for these experiments were modified from the orderable EVM specifically for the test cases discussed in this report and to allow for full dual-site capabilities. For any testing done with the orderable EVM only the bottom circuit (U2) can be used as drilling a hole at U1 would isolate the GND pin from the board.

GUID-20220725-SS0I-FRKR-CHFC-LNS4PQBKS3PM-low.jpgFigure 3-3 TPS7H2221-SEP Thermal Image for SEL.
GUID-20220727-SS0I-WB74-KHK2-ZRDRTQRQ2CJL-low.gifFigure 3-4 TPS7H2221EVM Schematic