SLVK158A November   2023  – June 2024 TPS7H6003-SP

PRODUCTION DATA  

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Single-Event Effects (SEE)
  6. 3 Device and Test Board Information
  7. 4 Irradiation Facility and Setup
  8. 5 Depth, Range, and LETEFF Calculation
  9. 6 Test Setup and Procedures
  10. 7 Destructive Single-Event Effects (DSEE)
    1. 7.1 Single-Event Latch-up (SEL) Results
    2. 7.2 Single-Event Burnout (SEB) and Single-Event Gate Rupture (SEGR) Results
  11. 8 Single-Event Transients (SET)
  12. 9 Event Rate Calculations
  13. 10Summary
  14.   A References
  15.   B Revision History

3 Device and Test Board Information

The TPS7H60x3-SP is packaged in a 48-pin ceramic package as shown in Figure 3-1. A TPS7H60X3-SP evaluation board made specifically for radiation testing was used to evaluate the performance and characteristics of the TPS7H60x3-SP under heavy ion radiation. The TPS7H60x3-SP evaluation board is shown in Figure 3-2. The board schematic is shown in Figure 3-3.

The package was delidded to reveal the die face for all heavy-ion testing.

TPS7H6003-SP Photograph of Delidded TPS7H6003-SP (Left) and Pinout Diagram (Right)Figure 3-1 Photograph of Delidded TPS7H6003-SP (Left) and Pinout Diagram (Right)
TPS7H6003-SP TPS7H60X3-SP EVM Top ViewFigure 3-2 TPS7H60X3-SP EVM Top View

Although not shown here, there are 1nF capacitors on the HO and LO outputs. See the block diagram for the setup of the capacitive load.

TPS7H6003-SP TPS7H60x3-SP Evaluation Board SchematicsFigure 3-3 TPS7H60x3-SP Evaluation Board Schematics