SLVK163 November   2023 TPS7H6003-SP

PRODUCTION DATA  

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Device Information
    1. 1.1 Product Description
    2. 1.2 Device Details
  5. 2Total Dose Test Setup
    1. 2.1 Test Overview
    2. 2.2 Test Description and Facilities
    3. 2.3 Test Setup Details
      1. 2.3.1 Unbiased
      2. 2.3.2 Biased
    4. 2.4 Test Configuration and Condition
  6. 3TID Characterization Test Results
    1. 3.1 TID Characerization Results Summary
    2. 3.2 Data Sheet Electrical Parameters
  7. 4Applicable and Reference Documents
    1. 4.1 Applicable Documents
    2. 4.2 Reference Documents
  8.   A Appendix: HDR TID Report

3.2 Data Sheet Electrical Parameters

Specifications are at ambient temperature TA = 25°C, VIN = 10 V to 14 V, VBP5L = VBP5H = 5 V, and no load on LOH, LOL, HOH, and HOL (unless otherwise noted).

Table 3-1 TPS7H6003-SP Data Sheet Electrical Parameters
Parameter Test Conditions MIN MAX UNIT Test Number
SUPPLY CURRENTS
IQLS Low-side quiescent current VIN = 12 V, BOOT = 10 V MODE = PWM, EN = 0 V 6.8 mA 35.0, 36.0, 37.0
MODE = IIM, LI = HI = 0 V 8 35.2, 36.2, 37.2
IQHS High-side quiescent current VIN = 12 V, BOOT = 10 V MODE = PWM, EN = 0 V 6.3 mA 35.1, 36.1, 37.1
MODE = IIM, LI = HI = 0 V 6.3 35.3, 36.3, 37.3
IOP_LS Low-side operating current MODE = PWM, no load for HOL and HOH f = 500 kHz 9 mA 35.6, 36.6, 37.6
f = 1 MHz 11 35.8, 36.8, 37.8
f = 2 MHz 16 35.10, 36.10, 37.10
f = 5 MHz 30 35.12, 36.12, 37.12
MODE = IIM, no load for HOL and HOH f = 500 kHz 9 35.14, 36.14, 37.14
f = 1 MHz 12 35.16, 36.16, 37.16
f = 2 MHz 17 35.18, 36.18, 37.18
f = 5 MHz 30 35.20, 36.20, 37.20
IOP_HS High-side operating current MODE = PWM, no load for HOL and HOH f = 500 kHz 6.5 mA 35.7, 36.7, 37.7
f = 1 MHz 8 35.9, 36.9, 37.9
f = 2 MHz 10.5 35.11, 36.11, 37.11
f = 5 MHz 17.5 35.13, 36.13, 37.13
MODE = IIM, no load for HOL and HOH f = 500 kHz 6.5 35.15, 36.15, 37.15
f = 1 MHz 8 35.17, 36.17, 37.17
f = 2 MHz 10.5 35.19, 36.19, 37.19
f = 5 MHz 15 35.21, 36.21, 37.21
GATE DRIVER
VOL Low-level output voltage IOL = 100 mA 0.15 V 45.0, 46.0, 47.0
BP5x – VOH High-level output voltage IOH = 100 mA 0.3 V 45.2, 46.2, 47.2
IOH Peak source current HOH, LOH = 0 V, BP5x = 5 V 0.7 2.3 A 50.0, 50.1, 51.0, 51.1, 52.0, 52.1
IOL Peak sink current HOL, LOL = 5 V, BP5x = 5 V 1.6 4.6 A 50.2, 51.2, 52.2
INTERNAL REGULATORS
VBP5L Low-side 5-V regulator output voltage CBP5L = 1 µF 4.75 5.175 V 60.1, 60.4, 60.7, 60.10, 60.13, 60.16, 60.19, 60.22, 61.1, 61.4, 61.7, 61.10, 61.13, 61.16, 61.19, 61.22, 62.1, 62.4, 62.7, 62.10, 62.13, 62.16, 62.19, 62.22
VBP5H High-side 5-V regulator output voltage CBP5H = 1 µF 4.75 5.175 V 60.2, 60.5, 60.8, 60.11, 60.14, 60.17, 60.20, 60.23, 61.2, 61.5, 61.8, 61.11, 61.14, 61.17, 61.20, 61.23, 62.2, 62.5, 62.8, 62.11, 62.14, 62.17, 62.20, 62.23
VBP7L 7-V regulator output voltage CBP7L = 1 µF 6.65 7.35 V 60.0, 60.3, 60.6, 60.9, 60.12, 60.15, 60.18, 60.21, 61.0, 61.3, 61.6, 61.9, 61.12, 61.15, 61.18, 61.21, 61.23, 62.0, 62.3, 62.6, 62.9, 62.12, 62.15, 62.18, 62.21
UNDERVOLTAGE PROTECTION
BP5HR BP5H UVLO rising threshold CBP5H = 1 µF 4 4.5 V 85.1, 86.1, 87.1(1)
BP5HF BP5H UVLO falling threshold CBP5H = 1 µF 3.8 4.3 V 85.2, 86.2, 87.2(1)
BP5LR BP5L UVLO rising threshold CBP5L = 1 µF 4. 4.5 V 80.1, 81.1, 82.1(1)
BP5LF BP5L UVLO falling threshold CBP5L = 1 µF 3.8 4.3 V 80.2, 81.2, 82.2(1)
BP7LR BP7L UVLO rising threshold CBP7L = 1 µF 6.2 6.8 V 80.4, 81.4, 82.4(1)
BP7LF BP7L UVLO falling threshold CBP7L = 1 µF 5.9 6.5 V 80.5, 81.5, 82.5(1)
VINR VIN UVLO rising threshold 8 9 V 70
VINF VIN UVLO falling threshold 7.5 8.5 V 70.1
BOOTR BOOT UVLO rising threshold 6.6 7.4 V 75
BOOTF BOOT UVLO falling threshold 6.2 7 V 75.1
INPUT PINS
VIR Input rising edge threshold 1.80 2.65 V 90.0, 91.0, 92.0, 90.3, 91.3, 92.3
VIF Input falling edge threshold 1.15 1.85 V 90.1, 91.1, 92.1, 90.4, 91.4, 92.4
RPD Input pull-down resistance V = 2.15 V applied at input (EN_HI or PWM_LI) 100 400 kΩ 90.6, 90.7, 91.6, 91.7, 92.6, 92.7
PROGRAMMABLE DEAD TIME
TDLH LO off to HO on dead time MODE = PWM, LO falling to HO rising (90% to 10%), f ≤ 2 MHz RLH = 3.32 kΩ 0 10 ns 95.0, 95.5, 95.10, 96.0, 96.5, 96.10, 97.0, 97.5, 97.10
RLH = 11.8 kΩ 8 15.5 95.1, 95.6, 95.11, 96.1, 96.6, 96.11, 97.1, 97.6, 97.11
RLH = 21 kΩ 15.5 24 95.2, 95.7, 95.12, 96.2, 96.7, 96.12, 97.2, 97.7, 97.12
RLH = 52.3 kΩ 36 59 95.3, 95.8, 95.13, 96.3, 96.8, 96.13, 97.3, 97.8, 97.13
RLH = 105 kΩ 74 113.5 95.4, 95.9, 95.14, 96.4, 96.9, 96.14, 97.4, 97.9, 97.14
TDHL HO off to LO on dead time MODE = PWM, HO falling to LO rising (90% to 10%), f ≤ 2 MHz RHL = 7.87 kΩ 0 10 ns 95.19, 95.24, 95.29, 96.19, 96.24, 96.29, 97.19, 97.24, 97.29
RHL = 13.3 kΩ 6 15 95.20, 95.25, 95.30, 96.20, 96.25, 96.30, 97.20, 97.25, 97.30
RHL = 23.7 kΩ 16 24.5 95.21, 95.26, 95.31, 96.21, 96.26, 96.31, 97.21, 97.26, 97.31
RHL = 57.6 kΩ 44 61 95.22, 95.27, 95.32, 96.22, 96.27, 96.32, 97.22, 97.27, 97.32
RHL = 113 kΩ 86 125 95.23, 95.28, 95.33, 96.23, 96.28, 96.33, 97.23, 97.28, 97.33
BOOTSTRAP DIODE SWITCH
Bootstrap diode switch parallel resistance IBST_SW = 1 mA 0.8 1.2 kΩ 100.1, 101.1, 102.1
POWER GOOD
Logic-low output IFLT= 1 mA 0.4 V 105.0, 106.0, 107.0
PGOOD internal resistance BP5L = 5 V, BP7L = 7 V, VIN = 12 V 0.7 1.9 MΩ 105.2, 106.2, 107.2
Minimum BP5L voltage for valid PGOOD output 2.45 V 105.1, 106.1, 107.1
(1) Tests are only tested in production or SPI Test Mode.

Table 3-2 TPS7H6003-SP Switching Characteristics
Parameter Test Conditions MIN MAX UNIT Test Number
tLPHL LO turnoff propagation delay MODE = PWM PWM rising to LOL falling 48 ns 110.0, 111.0, 112.0
MODE = IIM LI falling to LOL falling 38 ns 110.3, 110.7, 111.3, 111.7, 112.3, 112.7
tLPLH LO turnon propagation delay MODE = IIM LI rising to LOH rising 38 ns 110.2, 110.6, 111.2, 111.6, 112.2, 112.6
tHPHL HO turnoff propagation delay MODE = PWM PWM falling to HOL falling 50 ns 110.1, 111.1,112.1
MODE = IIM HI falling to HOL falling 40 110.5, 110.9, 111.5, 111.9, 112.5, 112.9
tHPLH HO turnon propagation delay MODE = IIM HI rising to HOH rising 40 ns 110.4, 110.8, 111.4, 111.8, 112.4, 112.8
tMON Delay matching LO on and HO off MODE = IIM 12 ns 110.1, 111.1, 112.1, 110.12, 111.12, 112.12
tMOFF Delay matching LO off and HO on MODE = IIM 4 ns 110.11, 110.13, 111.11, 111.13, 112.11, 112.13
tHRC HO rise time CL = 1000 pF 10% to 90% 7.5 ns 115, 116, 117
tLRC LO rise time 7.5 ns 115.2, 116.2, 117.2
tHFC HO fall time 90% to 10% 5.5 ns 115.1, 116.1, 117.1
tLFC LO fall time 5.5 ns 115.3, 116.3, 117.3
tPW_IIM Minimum input pulse width (turn-on) MODE = IIM 8 ns 120, 120.2, 120.4, 121, 121.2, 121.4, 122, 122.2, 122.4
tPW_IIM_OFF Minimum input pulse width (turn-off) MODE = IIM 12 ns 120.1, 120.3, 120.5, 121.1, 121.3, 121.5, 122.1, 122.3, 122.5