SLVK173 July   2024 TPS7H4011-SP

 

  1.   1
  2.   TPS7H4011-SP Single-Event Effects (SEE)
  3.   Trademarks
  4. 1 Introduction
  5. 2 Single-Event Effects (SEE)
  6. 3 Device and Test Board Information
  7. 4 Irradiation Facility and Setup
  8. 5 Depth, Range, and LETEFF Calculation
  9. 6 Test Setup and Procedures
  10. 7 Destructive Single-Event Effects (DSEE)
    1. 7.1 Single-Event Latch-up (SEL) Results
    2. 7.2 Single-Event Burnout (SEB) and Single-Event Gate Rupture (SEGR) Results
  11. 8 Single-Event Transients (SET)
  12. 9 Event Rate Calculations
  13. 10Summary
  14.   A Total Ionizing Dose from SEE Experiments
  15.   B References

2 Single-Event Effects (SEE)

The primary concern for the TPS7H4011-SP is the robustness against the destructive single-event effects (DSEE): single-event latch-up (SEL), single-event burnout (SEB), and single-event gate rupture (SEGR). In mixed technologies such as the BiCMOS process used on the TPS7H4011-SP, the CMOS circuitry introduces a potential for SEL susceptibility.

SEL can occur if excess current injection caused by the passage of an energetic ion is high enough to trigger the formation of a parasitic cross-coupled PNP and NPN bipolar structure (formed between the p-sub and n-well and n+ and p+ contacts) (1,2). The parasitic bipolar structure initiated by a single-event creates a high-conductance path (inducing a steady-state current that is typically orders-of-magnitude higher than the normal operating current) between power and ground that persists (is latched) until power is removed, the device is reset, or until the device is destroyed by the high-current state. The TPS7H4011-SP was tested for SEL at the maximum recommended input voltage (VIN) of 14V. The output load was configured to provide a constant resistance value of 0.2718Ω to create a 12A load on the output. During testing of the four devices, the TPS7H4011-SP did not exhibit any SEL with heavy-ions with LETEFF = 75MeV × cm2 / mg at flux of approximately 5 × 104 ions / cm2 × s, fluence of approximately 107 ions / cm2, and a die temperature of ~125°C.

The TPS7H4011-SP was evaluated for SEB/SEGR at a maximum voltage of 14V in enabled and disabled mode. Because it has been shown that the MOSFET susceptibility to burnout decrement with temperature (5), the device was evaluated while operating under room temperatures. The device was tested with no external thermal control device. During the SEB/SEGR testing, not a single current event was observed, demonstrating that the TPS7H4011-SP is SEB/SEGR-free up to LETEFF = 75MeV × cm2/ mg at a flux of approximately 5 × 104 ions / cm2× s, fluences of approximately 107 ions / cm2, and a die temperature of approximately 25°C.

The TPS7H4011-SP was characterized at VIN of 5V and 12V. During SET testing the VOUT, SS_TR, and PWRGD signals were monitored. During the SET testing, not a single transient was observed, demonstrating that the TPS7H4011-SP is SET/SEFI-free up to LETEFF = 75MeV × cm2/ mg at a flux of approximately 5 × 104 ions / cm2× s, fluences of approximately 107 ions / cm2, and a die temperature of approximately 25°C. For more details on the SET testing of the TPS7H4011-SP, see Single-Event Transients (SET).