5 Depth, Range, and LET_EFF Calculation

Figure 5-1 Generalized Cross-Section of the LBC7 Technology BEOL Stack on the TPS7H1121-SP [Top] and Key Ion Parameters [Bottom]

The TPS7H1121-SP is fabricated in the TI Linear BiCMOS 250-nm process with a back-end-of-line (BEOL) stack consisting of 4 levels of standard thickness aluminum. The total stack height from the surface of the passivation to the silicon surface is 10.885-μm based on nominal layer thickness as shown in Figure 5-1. Accounting for energy loss through the 1-mil thick Aramica beam port window, the 70-mm air gap, and the BEOL stack over the TPS7H1121-SP, the effective LET (LET_EFF) at the surface of the silicon substrate and the depth was determined with information provided by the MSU FRIB. The results are shown in Ion LET_EFF, Depth, and Range in Silicon.