The TPS7H5002-SP QMLP is a single output radiation-tolerant PWM controller that supports buck applications and single ended isolated topologies. The controller ontains an integrated synchronous rectification output. Optimized for GaN power semiconductor based applications, the controller has configurable dead time and configurable leading edge blank time. The controller can be configured for maximum duty cycle of 75% or 100%. As such, the DCL pin can be left floating or connected to VLDO. Connection of the DCL pin to AVSS is not permissible for this device. The TPS7H5002-SP QMLP features dead-time and leading edge blank time programmability to target high-efficiency and high-performance topologies 0.613V ±1% accurate internal reference allows design of high-current buck converters for FPGA core voltages.

The TPS7H5002-SP QMLP can be driven using an external clock through the SYNC pin or run using the internal oscillator at a frequency programmed by the user. Other programmable features include the UVLO threshold, soft start, and slope compensation. The TPS7H5002-SP QMLP is packaged in a very small 24-pin TSSOP (thin-shrink small outline package) package.