SLVK176 August 2024 TPS7H5003-SP
| PARAMETER | TEST CONDITION | TPS7H5003-SP QMLP DATA SHEET | TEST # | |||
|---|---|---|---|---|---|---|
| MIN | TYP | MAX | UNIT | |||
| SUPPLY VOLTAGES AND CURRENTS | ||||||
| IDD Operating supply current | fSW = 500 kHz, No load for OUTA, OUTB, SRA, and SRB | 6.25 | 8 | mA | 5.24 __IDD_ACT_500K_NOLOAD_4V, 5.25 __IDD_ACT_500K_NOLOAD_5V, 5.26 __IDD_ACT_500K_NOLOAD_12V, 5.27 __IDD_ACT_500K_NOLOAD_14V | |
| fSW = 1 MHz, No load for OUTA, OUTB, SRA, and SRB | 6.75 | 9.5 | mA | 5.28 __IDD_ACT_1M_NOLOAD_4V, 5.29 __IDD_ACT_1M_NOLOAD_5V, 5.30 __IDD_ACT_1M_NOLOAD_12V, 5.31 __IDD_ACT_1M_NOLOAD_14V | ||
| fSW = 2 MHz, No load for OUTA, OUTB, SRA, and SRB | 8.5 | 13.5 | mA | 5.36 __IDD_ACT_2M_NOLOAD_4V, 5.37 __IDD_ACT_2M_NOLOAD_5V, 5.38 __IDD_ACT_2M_NOLOAD_12V, 5.39 __IDD_ACT_2M_NOLOAD_14V | ||
fSW = 500 kHz, CLOAD = 100pF for OUTA, OUTB, SRA, and SRB | 7.5 | 9.5 | mA | 5.48 __IDD_ACT_500K_4V, 5.49 __IDD_ACT_500K_5V, 5.50 __IDD_ACT_500K_12V, 5.51 __IDD_ACT_500K_14V | ||
| fSW = 1 MHz, CLOAD = 100pF for OUTA, OUTB, SRA, and SRB | 9 | 12 | mA | 5.52 __IDD_ACT_1M_4V, 5.53 __IDD_ACT_1M_5V, 5.54 __IDD_ACT_1M_12V, 5.55 __IDD_ACT_1M_14V | ||
| fSW = 2 MHz, CLOAD = 100pF for OUTA, OUTB, SRA, and SRB | 14 | 19.5 | mA | 5.60 __IDD_ACT_2M_4V, 5.61 __IDD_ACT_2M_5V, 5.62 __IDD_ACT_2M_12V, 5.63 __IDD_ACT_2M_14V | ||
IDD(dis) Standby current | EN = 0 V | 3 | mA | 5.1 __IDD_DIS_4V, 5.2 __IDD_DIS_5V, 5.3 __IDD_DIS_12V 5.4 __IDD_DIS_14V | ||
VLDO Internal linear regulator output voltage | 5 V ≤VIN ≤ 14 V, fsw ≤ 1 MHz | 4.75 | 5 | 5.2 | V | 5.65 __V_LDO_100K_5V, 5.66 __V_LDO_100K_12V, 5.67 __V_LDO_100K_14V, 5.69 __V_LDO_200K_5V, 5.70 __V_LDO_200K_12V, 5.71 __V_LDO_200K_14V, 5.73 __V_LDO_500K_5V, 5.74 __V_LDO_500K_12V, 5.75 __V_LDO_500K_14V, 5.77 __V_LDO_1M_5V, 5.78 __V_LDO_1M_12V, 5.79 __V_LDO_1M_14V |
5 V ≤ VIN ≤ 14 V, fsw = 2 MHz | 4.65 | 5 | 5.2 | V | 5.85 __V_LDO_2M_5V, 5.86 __V_LDO_2M_12V, 5.87 __V_LDO_2M_14V | |
| ENABLE AND UNDERVOLTAGE LOCKOUT | ||||||
VENR EN threshold rising | 0.57 | 0.6 | 0.65 | V | 6.5 __V_EN_RISE_4V, 6.8 __V_EN_RISE_5V, 6.11 __V_EN_RISE_12V, 6.14 __V_EN_RISE_14V | |
| VENF EN threshold falling | 0.47 | 0.5 | 0.55 | V | 6.6 __V_EN_FALL_4V, 6.9 __V_EN_FALL_5V, 6.12 __V_EN_FALL_12V, 6.15 __V_EN_FALL_14V | |
| VENH EN hysteresis voltage | 85 | 95 | 105 | mV | 6.7 __V_EN_HYS_4V, 6.10 __V_EN_HYS_5V, 6.13 __V_EN_HYS_12V, 6.16 __V_EN_HYS_14V | |
IEN EN pin input leakage current | VIN = 14 V, EN = 5V | 5 | 50 | nA | 6.1 __I_EN_LEAK_4V, 6.2 __I_EN_LEAK_5V, 6.3 __I_EN_LEAK_12V, 6.4 __I_EN_LEAK_14V | |
VLDOUVLOR VLDO UVLO rising | 3.44 | 3.55 | 3.66 | V | 6.34 __UVLO_VLDO_RISE_1MHz, 6.37 __UVLO_VLDO_RISE_100kHz, 6.40 __UVLO_VLDO_RISE_200kHz, 6.43 __UVLO_VLDO_RISE_500kHz, 6.46 __UVLO_VLDO_RISE_2MHz | |
| VLDOUVLOF VLDO UVLO falling | 3.29 | 3.4 | 3.51 | V | 6.35 __UVLO_VLDO_FALL_1MHz, 6.38 __UVLO_VLDO_FALL_100kHz, 6.41 __UVLO_VLDO_FALL_200kHz, 6.44 __UVLO_VLDO_FALL_500kHz, 6.47 __UVLO_VLDO_FALL_2MHz | |
| VLDOUVLOH VLDO UVLO hysteresis | 115 | 135 | 160 | mV | 6.36 __UVLO_VLDO_HYS_1MHz, 6.39 __UVLO_VLDO_HYS_100kHz, 6.42 __UVLO_VLDO_HYS_200kHz, 6.45 __UVLO_VLDO_HYS_500kHz, 6.48 __UVLO_VLDO_HYS_2MHz | |
| SOFT START | ||||||
ISS Soft-start current | SS = 0.3 V | 1.98 | 2.7 | 3.32 | μA | 7.1 __I_SS_4V, 7.3 __I_SS_5V, 7.5 __I_SS_12V, 7.7 __I_SS_14V |
| ERROR AMPLIFIER | ||||||
EAgm Transconductance | –2 μA < ICOMP < 2 μA, V(COMP) = 1 V | 1150 | 1800 | 2500 | μA/V | 8.9 __EA_GM_4V, 8.10 __EA_GM_5V, 8.11 __EA_GM_12V, 8.12 __EA_GM_14V |
EAISRC Error amplifier source current | V(COMP) = 1 V, 100-mV input overdrive | 100 | 190 | μA | 8.13 __EA_I_SOURCE_4V, 8.14 __EA_I_SOURCE_5V, 8.15 __EA_I_SOURCE_12V, 8.16 __EA_I_SOURCE_14V | |
EAISNK Error amplifier sink current | V(COMP) = 1 V, 100-mV input overdrive | 100 | 190 | μA | 8.17 __EA_I_SINK_4V, 8.18 __EA_I_SINK_5V, 8.19 __EA_I_SINK_12V, 8.20 __EA_I_SINK_14V | |
EAOS Error amplifier offset voltage | –2 | 2 | mV | 8.5 __EA_OS_4V, 8.6 __EA_OS_5V, 8.7 __EA_OS_12V, 8.8 __EA_OS_14V | ||
| OSCILLATOR | ||||||
SYNCRT SYNC out low-to-high rise time (10%/90%) | CLOAD = 25 pF | 6 | 15 | ns | 9.1 __T_SYNC_RISE_100kHz_4V, 9.5 __T_SYNC_RISE_200kHz_4V, 9.9 __T_SYNC_RISE_500kHz_4V, 9.13 __T_SYNC_RISE_1MHz_4V, 9.17 __T_SYNC_RISE_1p5MHz_4V, 9.21 __T_SYNC_RISE_2MHz_4V, 9.25 __T_SYNC_RISE_100kHz_5V, 9.29 __T_SYNC_RISE_200kHz_5V, 9.33 __T_SYNC_RISE_500kHz_5V, 9.37 __T_SYNC_RISE_1MHz_5V, 9.41 __T_SYNC_RISE_1p5MHz_5V, 9.45 __T_SYNC_RISE_2MHz_5V, 9.49 __T_SYNC_RISE_100kHz_12V, 9.53 __T_SYNC_RISE_200kHz_12V, 9.57 __T_SYNC_RISE_500kHz_12V, 9.61 __T_SYNC_RISE_1MHz_12V, 9.65 __T_SYNC_RISE_1p5MHz_12V, 9.69 __T_SYNC_RISE_2MHz_12V, 9.73 __T_SYNC_RISE_100kHz_14V, 9.77 __T_SYNC_RISE_200kHz_14V, 9.81 __T_SYNC_RISE_500kHz_14V, 9.85 __T_SYNC_RISE_1MHz_14V, 9.89 __T_SYNC_RISE_1p5MHz_14V, 9.93 __T_SYNC_RISE_2MHz_14V | |
SYNCFT SYNC out high-to-low fall time (10%/90%) | CLOAD = 25 pF | 6 | 17 | ns | 9.2 __T_SYNC_FALL_100kHz_4V, 9.14 __T_SYNC_FALL_1MHz_4V, 9.22 __T_SYNC_FALL_2MHz_4V, 9.26 __T_SYNC_FALL_100kHz_5V, 9.38 __T_SYNC_FALL_1MHz_5V, 9.46 __T_SYNC_FALL_2MHz_5V, 9.74 __T_SYNC_FALL_100kHz_14V, 9.86 __T_SYNC_FALL_1MHz_14V, 9.94 __T_SYNC_FALL_2MHz_14V | |
SYNCOL SYNC out low level | IOL= 10 mA | 500 | mV | 9.186__SYNC_VOL_4V, 9.187__SYNC_VOL_5V, 9.188__SYNC_VOL_12V, 9.189__SYNC_VOL_14V | ||
EXTDT Externally set frequency detection time | RT = Open, f = 200 kHz | 20 | μs | 9.185__T_SYNC_DETECT | ||
FSWEXT Externally set frequency | RT = 1.07 MΩ | 95 | 105 | 115 | kHz | 9.4 __FSW_EXT_RT_100kHz_4V, 9.28 __FSW_EXT_RT_100kHz_5V, 9.52 __FSW_EXT_RT_100kHz_12V, 9.76 __FSW_EXT_RT_100kHz_14V |
RT = 511 kΩ | 190 | 210 | 230 | kHz | 9.8 __FSW_EXT_RT_200kHz_4V, 9.32 __FSW_EXT_RT_200kHz_5V, 9.56 __FSW_EXT_RT_200kHz_12V, 9.80 __FSW_EXT_RT_200kHz_14V | |
RT =90.9 kΩ | 900 | 1000 | 1100 | kHz | 9.16 __FSW_EXT_RT_1MHz_4V, 9.40 __FSW_EXT_RT_1MHz_5V, 9.64 __FSW_EXT_RT_1MHz_12V, 9.88 __FSW_EXT_RT_1MHz_14V | |
RT = 34.8 kΩ | 1700 | 2000 | 2300 | kHz | 9.24 __FSW_EXT_RT_2MHz_4V, 9.48 __FSW_EXT_RT_2MHz_5V, 9.72 __FSW_EXT_RT_2MHz_12V, 9.96 __FSW_EXT_RT_2MHz_14V | |
| VOLTAGE REFERENCE | ||||||
VREF Internal voltage reference initial tolerance | Measured at COMP, 25°C | 0.609 | 0.613 | 0.615 | V | 8.1 __VREF_4V, 8.2 __VREF_5V, 8.3 __VREF_12V, 8.4 __VREF_14V |
REFCAP REFCAP voltage | REFCAP = 470 nF | 1.213 | 1.225 | 1.237 | V | 5.88 __V_REFCAP_100K_4V, 5.89 __V_REFCAP_100K_5V, 5.90 __V_REFCAP_100K_12V, 5.91 __V_REFCAP_100K_14V, 5.92 __V_REFCAP_200K_4V, 5.93 __V_REFCAP_200K_5V, 5.94 __V_REFCAP_200K_12V, 5.95 __V_REFCAP_200K_14V, 5.96 __V_REFCAP_500K_4V, 5.97 __V_REFCAP_500K_5V, 5.98 __V_REFCAP_500K_12V, 5.99 __V_REFCAP_500K_14V, 5.100__V_REFCAP_1M_4V, 5.101__V_REFCAP_1M_5V, 5.102__V_REFCAP_1M_12V, 5.103__V_REFCAP_1M_14V, 5.104__V_REFCAP_1P5M_4V, 5.105__V_REFCAP_1P5M_5V, 5.106__V_REFCAP_1P5M_12V, 5.107__V_REFCAP_1P5M_14V, 5.108__V_REFCAP_2M_4V, 5.109__V_REFCAP_2M_5V, 5.110__V_REFCAP_2M_12V, 5.111__V_REFCAP_2M_14V |
| CURRENT SENSE, CURRENT LIMIT, AND HICCUP | ||||||
CCSR | COMP to CS_ILIM ratio | 2.00 | 2.06 | 2.12 | 10.49 __CCSR_Ratio | |
VCS_ILIM Current limit (over-current) threshold | 1.05 | 1.09 | V | 10.1 __V_CS_ILIM_OC_Rise_4V, 10.3 __V_CS_ILIM_OC_Rise_5V, 10.5 __V_CS_ILIM_OC_Rise_12V, 10.7 __V_CS_ILIM_OC_Rise_14V | ||
| FAULT | ||||||
VFLTR FLT threshold rising | 0.57 | 0.6 | 0.65 | V | 12.1 __V_FAULT_RISE_4V, 12.4 __V_FAULT_RISE_5V, 12.7 __V_FAULT_RISE_12V, 12.10 __V_FAULT_RISE_14V | |
VFLTF FLT threshold falling | 0.47 | 0.5 | 0.55 | V | 12.2 __V_FAULT_FALL_4V, 12.5 __V_FAULT_FALL_5V, 12.8 __V_FAULT_FALL_12V, 12.11 __V_FAULT_FALL_14V | |
| VFLTH FLT hysteresis voltage | 90 | 100 | 110 | mV | 12.3 __V_FAULT_HYS_4V, 12.6 __V_FAULT_HYS_5V, 12.9 __V_FAULT_HYS_12V, 12.12 __V_FAULT_HYS_14V | |
TFLT FLT minimum pulse width | VFLT = 1 V | 0.4 | 1.4 | μs | 12.14 __T_FAULT_MIN | |
tDFLT FLT delay duration | fsw = 100 kHz | 140 | 152 | 169 | μs | 12.15 __T_FAULT_DELAY_100kHz |
| fsw = 200 kHz | 66 | 78 | 86 | μs | 12.17 __T_FAULT_DELAY_200kHz | |
| fsw = 1 MHz | 14 | 17 | 21 | μs | 12.21 __T_FAULT_DELAY_1MHz | |
| fsw = 2 MHz | 7 | 11 | 14 | μs | 12.23 __T_FAULT_DELAY_2MHz | |
| PRIMARY AND SYNCHRONOUS RECTIFIER OUTPUTS | ||||||
Rise/fall time | RLOAD = 50 kΩ, CLOAD = 100 pF, 10% to 90% | 10 | 17 | ns | 13.1 __OUTA_RISE_1MHz_4V, 13.9 __OUTA_RISE_1MHz_5V, 13.17 __OUTA_RISE_1MHz_12V, 13.25 __OUTA_RISE_1MHz_14V, 13.3 __OUTA_FALL_1MHz_4V, 13.11 __OUTA_FALL_1MHz_5V, 13.19 __OUTA_FALL_1MHz_12V, 13.27 __OUTA_FALL_1MHz_14V | |
tMIN Minimum on-time | 5 V ≤ VIN ≤ 14 V | 115 | ns | 13.145__OUT_T_ON_MIN | ||
TDPS Primary off to secondary on dead time | 5 V ≤ VIN ≤ 14 V, 90% of OUTx falling to 10% of SRx rising, OUTx and SRx floating | 40 | 50 | 60 | ns | 13.53 __PSA_DT_50ns_1M_5V, 13.57 __PSA_DT_50ns_1M_12V, 13.61 __PSA_DT_50ns_1M_14V, |
TDSP Secondary off to primary on dead time | 5 V ≤ VIN ≤ 14 V, 90% of SRx falling to 10% of OUTx rising edge, OUTx and SRx floating | 40 | 50 | 60 | ns | 13.55 __SPA_DT_50ns_1M_5V, 13.59 __SPA_DT_50ns_1M_12V, 13.63 __SPA_DT_50ns_1M_14V |
| DUTY CYCLE | ||||||
| DMAX Maximum duty cycle | DCL = floating | 70 | 75 | 80 | % | 13.163__MAX_DC_DCL_OPEN |
DCL =VLDO | 100 | % | 13.166__MAX_DC_DCL_VLDO | |||