SLVS754D March   2007  – January 2015 TPS65053

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Dissipation Ratings
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Power Save Mode
        1. 7.3.1.1 Dynamic Voltage Positioning
        2. 7.3.1.2 Soft Start
        3. 7.3.1.3 100% Duty Cycle Low Dropout Operation
        4. 7.3.1.4 Undervoltage Lockout
      2. 7.3.2 Mode Selection
      3. 7.3.3 Enable
      4. 7.3.4 Dynamic Ouput Voltage Scaling
      5. 7.3.5 RESET on the TPS65053x
      6. 7.3.6 RESET Generation and Output Monitoring on the TPS65058
      7. 7.3.7 Short-Circuit Protection
      8. 7.3.8 Thermal Shutdown
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 DCDC Output Voltage Setting
        2. 8.2.2.2 LDO Output Voltage Setting
        3. 8.2.2.3 Low Dropout Voltage Regulators
        4. 8.2.2.4 DCDC Output Filter Design (Inductor and Output Capacitor)
          1. 8.2.2.4.1 Inductor Selection
          2. 8.2.2.4.2 Output Capacitor Selection
        5. 8.2.2.5 DCDC Input Capacitor Selection
        6. 8.2.2.6 Sequencing and Output Logic Signal RESET
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Related Links
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

10 Layout

10.1 Layout Guidelines

  • The input capacitors for the DCDC converters should be placed as close as possible to the VINDCDC1/2 pin and the PGND1 and PGND2 pins.
  • The inductor of the output filter should be placed as close as possible to the device to provide the shortest switch node possible, reducing the noise emitted into the system and increasing the efficiency.
  • Sense the feedback voltage from the output at the output capacitors to ensure the best DC accuracy. Feedback should be routed away from noisey sources such as the inductor. If possible route on the opposing side as the swiitch node and inductor and place a GND plane between the feedback and the noisey sources or keepout underneath them entirely.
  • Place the output capacitors as close as possible to the inductor to reduce the feedback loop as much as possible. This will ensure best regulation at the feedback point.
  • Place the device as close as possible to the the most demanding or sensitive load. The output capacitors should be placed close to the input of the load. This will ensure the best AC performance possible.
  • The input and output capacitors for the LDOs should be placed close to the device for best regulation performance.
  • The use a one common ground plane is recommended for the device layout. The AGND can be separated from the PGND but, a large low parasitic PGND is required to connect the PGNDx pins to the CIN and external PGND connections.

10.2 Layout Example

Layout.gifFigure 28. Layout Example Schematic for TPS65053