SLVS754D March   2007  – January 2015 TPS65053

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Dissipation Ratings
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Power Save Mode
        1. 7.3.1.1 Dynamic Voltage Positioning
        2. 7.3.1.2 Soft Start
        3. 7.3.1.3 100% Duty Cycle Low Dropout Operation
        4. 7.3.1.4 Undervoltage Lockout
      2. 7.3.2 Mode Selection
      3. 7.3.3 Enable
      4. 7.3.4 Dynamic Ouput Voltage Scaling
      5. 7.3.5 RESET on the TPS65053x
      6. 7.3.6 RESET Generation and Output Monitoring on the TPS65058
      7. 7.3.7 Short-Circuit Protection
      8. 7.3.8 Thermal Shutdown
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 DCDC Output Voltage Setting
        2. 8.2.2.2 LDO Output Voltage Setting
        3. 8.2.2.3 Low Dropout Voltage Regulators
        4. 8.2.2.4 DCDC Output Filter Design (Inductor and Output Capacitor)
          1. 8.2.2.4.1 Inductor Selection
          2. 8.2.2.4.2 Output Capacitor Selection
        5. 8.2.2.5 DCDC Input Capacitor Selection
        6. 8.2.2.6 Sequencing and Output Logic Signal RESET
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Related Links
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

RGE Package - TPS65053x
24 Pins
Top View
po_lvs754.gif
RGE Package - TPS65058
24 Pins
Top View
po_lvs851.gif

Pin Functions

PIN I/O DESCRIPTION
NAME TPS65053, TPS650531, TPS650532 TPS65058
AGND 24 24 I Analog GND, connect to PGND and PowerPAD™
DEF_DCDC2 — 5 I Switches output votlage at DCDC2, logic HIGH = 1.8V, logic LOW = 1.2V
DEF_LDO — 4 I Switches output votlage at LDO2, logic HIGH = 1.8V, logic LOW = 1.2V
Switches output votlage at LDO3, logic HIGH = 1.8V, logic LOW = 1.3V
EN_DCDC1 20 20 I Enable Input for converter 1, active high
EN_DCDC2 21 21 I Enable Input for converter 2, active high
EN_LDO1 22 22 I Enable input for LDO1. Logic high enables the LDO, logic low disables the LDO.
EN_LDO2 11 11 I Enable input for LDO2. Logic high enables the LDO, logic low disables the LDO.
EN_LDO3 12 12 I Enable input for LDO3. Logic high enables the LDO, logic low disables the LDO.
FB_DCDC1 19 19 I Input to adjust output voltage of converter 1 between 0.6 V and VI. Connect external resistor divider between VOUT1, this pin and GND.
FB_DCDC2 13 13 I Input to adjust output voltage of converter 2 between 0.6V and VIN. Connect external resistor divider between VOUT2, this pin and GND.
FB_LDO1 4 — 1 Feedback input for the external voltage divider.
FB_LDO2 6 — I Feedback input for the external voltage divider.
L1 17 17 O Switch pin of converter 1. Connected to Inductor
L2 15 15 O Switch Pin of converter 2. Connected to Inductor.
MODE 23 23 I Select between Power Save Mode and forced PWM Mode for DCDC1 and DCDC2. In Power Save Mode, PFM is used at light loads, PWM for higher loads. If PIN is set to high level, forced PWM Mode is selected. If Pin has low level, then the device operates in Power Save Mode.
PGND1 18 18 I GND for converter 1
PGND2 14 14 I GND for converter 2
PowerPAD™ — — — Connect to GND
VCC 1 1, 6 I Power supply for digital and analog circuitry of DCDC1, DCDC2 and LDOs. This pin must be connected to the same voltage supply as VINDCDC1/2.
VINDCDC1/2 16 16 I Input voltage for VDCDC1 and VDCDC2 step-down converter. This must be connected to the same voltage supply as VCC.
VINLDO1 2 2 I Input voltage for LDO1
VINLDO2/3 8 8 I Input voltage for LDO2 and LDO3
VLDO1 3 3 O Output voltage of LDO1
VLDO2 7 7 O Output voltage of LDO2
VLDO3 9 9 O Output voltage of LDO3
THRESHOLD 5 — I Reset input
RESET 10 10 O Open drain active low reset output, 100 ms reset delay time.