SLVS813C June   2008  – November 2016 UCD9081

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Recommended Operating Conditions
    3. 6.3 Thermal Information
    4. 6.4 Electrical Characteristics
    5. 6.5 Timing Requirements: I2C Interface
    6. 6.6 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Rail Configuration
      2. 8.3.2 Graphical User Interface (GUI)
    4. 8.4 Device Functional Modes
      1. 8.4.1  Power Supply Sequencing
      2. 8.4.2  Power-Supply Enables
      3. 8.4.3  General-Purpose Outputs
      4. 8.4.4  Device Reset
      5. 8.4.5  Voltage Reference
      6. 8.4.6  Voltage Monitoring
      7. 8.4.7  Rail Shutdown
      8. 8.4.8  Alarm Processing
        1. 8.4.8.1 Ignore
        2. 8.4.8.2 Log Only
        3. 8.4.8.3 Retry n Times
        4. 8.4.8.4 Retry Continuously
        5. 8.4.8.5 Sequence
        6. 8.4.8.6 Sequence After Shutdown
      9. 8.4.9  Error Logging
      10. 8.4.10 Brownout
    5. 8.5 Programming
      1. 8.5.1 I2C Interface
      2. 8.5.2 Configuring and Monitoring the UCD9081
      3. 8.5.3 Resetting the Flash Error Log
      4. 8.5.4 Configuring the UCD9081
      5. 8.5.5 User Data
      6. 8.5.6 I2C Address Selection
      7. 8.5.7 I2C Transactions
        1. 8.5.7.1 I2C Unidirectional Transfer
        2. 8.5.7.2 I2C Combined Format
    6. 8.6 Register Maps
      1. 8.6.1  Register Descriptions
      2. 8.6.2  RAIL
      3. 8.6.3  ERROR
      4. 8.6.4  STATUS
      5. 8.6.5  VERSION
      6. 8.6.6  RAILSTATUS
      7. 8.6.7  FLASHLOCK
      8. 8.6.8  RESTART
      9. 8.6.9  WADDR and WDATA
      10. 8.6.10 Reading the FLASH Error Log
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Considerations for MONX Input Series Resistance, RS
      2. 9.1.2 Estimating UCD9081 Reporting Accuracy Over Variations in ADC Voltage Reference
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

RHB Package
32-Pin VQFN
Top View

Pin Functions

PIN(1) I/O DESCRIPTION
NAME NO.
ADDR2/GPO2 26 I/O I2C address select 2, general-purpose digital output 2
ADDR3/GPO3 27 I/O I2C address select 3, general-purpose digital output 3
ADDR4/GPO4 28 I/O I2C address select 4, general-purpose digital output 4
EN1 23 I/O Voltage rail 1 enable (digital output)
EN2 24 I/O Voltage rail 2 enable (digital output)
EN3 11 I/O Voltage rail 3 enable (digital output)
EN4 10 I/O Voltage rail 4 enable (digital output)
EN5 12 I/O Voltage rail 5 enable (digital output)
EN6 13 I/O Voltage rail 6 enable (digital output)
EN7 14 I/O Voltage rail 7 enable (digital output)
EN8/ADDR1/
GPO1		 25 I/O Voltage rail 8 enable (digital output), I2C address select 1, general-purpose digital output 1
MON1 6 I Analog input for voltage rail 1
MON2 7 I Analog input for voltage rail 2
MON3 8 I Analog input for voltage rail 3
MON4 18 I Analog input for voltage rail 4
MON5 19 I Analog input for voltage rail 5
MON6 9 I Analog input for voltage rail 6
MON7 15 I Analog input for voltage rail 7
MON8 16 I Analog input for voltage rail 8
NC 2 — Do not connect
NC 4, 17,
20, 31		 — Recommended to connect to VSS, pin is not connected internally
ROSC 32 — Internal oscillator frequency adjust. Must use 100-kΩ pullup to VCC for minimum drift and maximum frequency when sampling voltage rails.
RST 5 I Reset input
SCL 22 I/O I2C clock. Must pull up to 3.3 V.
SDA 21 I/O I2C data. Must pull up to 3.3 V.
TEST 29 I Connect to VSS
VCC 30 — Supply voltage
VSS 1 — Ground reference
XIN 3 — Connect to VCC
PowerPAD™ — — Package pad. Recommended to connect to VSS.
(1) Enable and GPIO pins are in high-impedance state when a device is received from factory and during the first configuration programming done by customer.