SLVSA92C November   2011  – September 2020 TPS63060 , TPS63061

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Power Good
      2. 8.3.2 Soft-Start Function
      3. 8.3.3 Short-Circuit Protection
      4. 8.3.4 Overvoltage Protection
      5. 8.3.5 Undervoltage Lockout
      6. 8.3.6 Overtemperature Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Buck-Boost Operation
      2. 8.4.2 Control Loop
      3. 8.4.3 Power-Save Mode
      4. 8.4.4 Synchronization
      5. 8.4.5 Dynamic Voltage Positioning
      6. 8.4.6 Dynamic Current Limit
      7. 8.4.7 Device Enable
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Step One: Output Filter Design
        2. 9.2.2.2 Step Two: Inductor Selection
        3. 9.2.2.3 Step Three: Capacitor Selection
          1. 9.2.2.3.1 Input Capacitors
          2. 9.2.2.3.2 Output Capacitor
          3. 9.2.2.3.3 Bypass Capacitor
        4. 9.2.2.4 Step Four: Setting the Output Voltage
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
  13. 13Mechanical, Packaging, and Orderable Information

8.4.4 Synchronization

Connecting a clock signal at PS/SYNC forces the device to synchronize to the connected clock frequency.

Synchronization is done by a PLL to lower and higher frequencies compared to the internal clock. The PLL can also tolerate missing clock pulses without the converter malfunctioning. The PS/SYNC input supports standard logic thresholds.