SLVSAR1E January   2011  – July 2015 DRV8833

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Fixed-Frequency PWM Motor Drivers
      2. 7.3.2 Bridge Control and Decay Modes
      3. 7.3.3 Current Control
      4. 7.3.4 nSLEEP Operation
      5. 7.3.5 Protection Circuits
        1. 7.3.5.1 Overcurrent Protection (OCP)
        2. 7.3.5.2 Thermal Shutdown (TSD)
        3. 7.3.5.3 Undervoltage Lockout (UVLO)
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Motor Voltage
        2. 8.2.2.2 Motor Current Trip Point
        3. 8.2.2.3 Sense Resistor
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
    2. 9.2 Power Supply and Logic Sequencing
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Heatsinking
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
      1. 10.3.1 Maximum Output Current
      2. 10.3.2 Thermal Protection
    4. 10.4 Power Dissipation
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

PWP Package
16-Pin HTSSOP
Top View
DRV8833 pwp_po_lvsar1.gif
PW Package
16-Pin TSSOP
Top View
DRV8833 pw_po_lvsar1.gif
RTY Package
16-Pin WQFN
Top View
DRV8833 rty_po1_lvsar1.gif

Pin Functions

PIN I/O(1) DESCRIPTION EXTERNAL COMPONENTS
OR CONNECTIONS
NAME WQFN HTSSOP,
TSSOP
POWER AND GROUND
GND 11
PPAD		 13 — Device ground. HTSSOP package has PowerPAD. Both the GND pin and device PowerPAD must be connected to ground.
VINT 12 14 — Internal supply bypass Bypass to GND with 2.2-μF, 6.3-V capacitor.
VM 10 12 — Device power supply Connect to motor supply. A 10-µF (minimum) ceramic bypass capacitor to GND is recommended.
VCP 9 11 IO High-side gate drive voltage Connect a 0.01-μF, 16-V (minimum) X7R ceramic capacitor to VM.
CONTROL
AIN1 14 16 I Bridge A input 1 Logic input controls state of AOUT1. Internal pulldown.
AIN2 13 15 I Bridge A input 2 Logic input controls state of AOUT2. Internal pulldown.
BIN1 7 9 I Bridge B input 1 Logic input controls state of BOUT1. Internal pulldown.
BIN2 8 10 I Bridge B input 2 Logic input controls state of BOUT2. Internal pulldown.
nSLEEP 15 1 I Sleep mode input Logic high to enable device, logic low to enter low-power sleep mode and reset all internal logic. Internal pulldown.
STATUS
nFAULT 6 8 OD Fault output Logic low when in fault condition (overtemperature, overcurrent)
OUTPUT
AISEN 1 3 IO Bridge A ground / ISENSE Connect to current sense resistor for bridge A, or GND if current control not needed
BISEN 4 6 IO Bridge B ground / ISENSE Connect to current sense resistor for bridge B, or GND if current control not needed
AOUT1 16 2 O Bridge A output 1 Connect to motor winding A
AOUT2 2 4 O Bridge A output 2
BOUT1 5 7 O Bridge B output 1 Connect to motor winding B
BOUT2 3 5 O Bridge B output 2
(1) I = Input, O = Output, OZ = Tri-state output, OD = Open-drain output, IO = Input/output