TPS4335x-Q1 Low IQ, Dual Synchronous Buck Controller

1 Features

Qualified for Automotive Applications
AEC-Q100 Test Guidance With the Following Results:
- Device Temperature Grade 1: –40°C to 125°C Ambient Operating Temperature
- Device HBM ESD Classification Level H2
- Device HBM CDM Classification Level C2
Two Synchronous Buck Controllers
Input Range up to 40 V (Transients up to 60 V)
Low-Power Mode I_Q: 30 µA (One Buck On), 35 µA (Two Bucks On)
Low Shutdown Current I_sh < 4 µA
Buck Output Range 0.9 V to 11 V
Programmable Frequency and External Synchronization Range 150 kHz to 600 kHz
Separate Enable Inputs (ENA, ENB)
Frequency Spread Spectrum (TPS43351-Q1)
Selectable Forced Continuous Mode or Automatic Low-Power Mode at Light Loads
Sense Resistor or Inductor DCR Sensing
Out-of-Phase Switching Between Buck Channels
Peak Gate Drive Current 1.5 A
Thermally Enhanced, 38-Pin HTSSOP (DAP) PowerPAD™ Package

2 Applications

Automotive Infotainment, Navigation, and Instrument Cluster Systems
Industrial or Automotive Multi-Rail DC Power Distribution Systems and Electronic Control Units

3 Description

The TPS43350-Q1 and TPS43351-Q1 include two current-mode synchronous buck controllers designed for the harsh environment in automotive applications. The devices are ideal for use in a multi-rail system with low quiescent requirements, as they automatically operate in low-power mode (consuming typically 30 µA) at light loads. The devices offer protection features such as thermal, soft-start, and overcurrent protection. During short-circuit conditions of the regulator output, activation of the current-foldback feature can limit the current through the MOSFETs for control of power dissipation. The two independent soft-start inputs allow ramp-up of the output voltage independently during start-up.

The programmable range of the switching frequency is from 150 kHz to 600 kHz, as is the frequency of an external clock to which the devices can synchronize. Additionally, the TPS43351-Q1 offers frequency-hopping spread-spectrum operation.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
TPS43350-Q1	HTSSOP (38)	12.50 mm × 6.20 mm
TPS43351-Q1	HTSSOP (38)	12.50 mm × 6.20 mm

For all available packages, see the orderable addendum at the end of the data sheet.

Typical Application Diagram

TPS43350-Q1 TPS43351-Q1 simp_blk_dia_front_SLVSAR7.gif

4 Revision History

Changes from D Revision (April 2013) to E Revision

Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section and Go
Changed typically 30 µA in Description section Go
Deleted the PACKAGE AND ORDERING INFORMATION section; see the POA at the end of the datasheetGo
Changed I/O to TYPE in Pin Functions and clarified GND for pins AGND, PGNDA, and PGNDB and to PWR for pins VBAT and VINGo
Changed description for PGA and PGB pinsGo
Added description for Gate-driver supply in Absolute Maximum Ratings tableGo
Changed 1.7 and 1.8 TYP and MAX columns to span rows Go
Changed 1.9 Shutdown current TYP to 3 and MAX to 5Go
Added inductor ripple current equationGo
Changed Layout Guidelines text Go

Changes from C Revision (September 2012) to D Revision

Changed pinout diagramGo
Revised Absolute Maximum Ratings tableGo

Changes from B Revision (June 2011) to C Revision

Changed input-voltage value for pins ENA and ENBGo
Added a sentence to EXTSUP pin descriptionGo
Corrected AEC specification in ESD ratingsGo
Multiple changes throughout Electrical Characteristics tableGo
Changed upper threshold voltage for ENx pins to 1.7 VGo
Text deletion from second paragraph of Light-Load PFM Mode sectionGo
Changed value of gate-driver decoupling capacitorGo
Added upper voltage limit for EXTSUP pinGo
Replaced paragraphs following the figure at end of Gate-Driver Supply sectionGo
Revised diagram of Simplified Application Schematic ExampleGo
Clarified parameter definition in Application Example tableGo
Added equations for Output Capacitor C_OUTA sectionGo
Added equations for BuckB Component Selection sectiionGo
Changed peak output current in BuckX High-Side and Low-Side N-Channel MOSFETs sectionGo

5 Pin Configuration and Functions

DAP Package

38-Pin HTSSOP With PowerPAD

Top View

Pin Functions

NAME	NO.	TYPE	DESCRIPTION
AGND	19, 23	GND	Analog ground reference
CBA	5	I	A capacitor on this pin acts as the voltage supply for the high-side N-channel MOSFET gate-drive circuitry in buck controller BuckA. When the buck is in a dropout condition, the device automatically reduces the duty cycle of the high-side MOSFET to approximately 95% on every fourth cycle to allow the capacitor to recharge.
CBB	34	I	A capacitor on this pin acts as the voltage supply for the high-side N-channel MOSFET gate-drive circuitry in buck controller BuckB. When the buck is in a dropout condition, the device automatically reduces the duty cycle of the high-side MOSFET to approximately 95% on every fourth cycle to allow the capacitor to recharge.
COMPA	13	O	Error amplifier output of BuckA and compensation node for voltage-loop stability. The voltage at this node sets the target for the peak current through the inductor of BuckA. Clamping his voltage on the upper and lower ends provides current-limit protection for the external MOSFETs.
COMPB	26	O	Error amplifier output of BuckB and compensation node for voltage-loop stability. The voltage at this node sets the target for the peak current through the inductor of BuckB. Clamping his voltage on the upper and lower ends provides current-limit protection for the external MOSFETs.
DLYAB	21	O	The capacitor at the DLYAB pin sets the power-good delay interval used to de-glitch the outputs of the power-good comparators. Leaving this pin open sets the power-good delay to an internal default value of 20 µs typical.
ENA	16	I	Enable input for BuckA (active-high with an internal pullup current source). An input voltage higher than 1.7 V enables the controller, whereas an input voltage lower than 0.7 V disables the controller. When both ENA and ENB are low, the device shuts down and consumes less than 4 µA of current.
ENB	17	I	Enable input for BuckB (active-high with an internal pullup current source). An input voltage higher than 1.7 V enables the controller, whereas an input voltage lower than 0.7 V disables the controller. When both ENA and ENB are low, the device shuts down and consumes less than 4 µA of current.
EXTSUP	37	I	One can use EXTSUP to supply the VREG regulator from one of the TPS43350-Q1 or TPS43351-Q1 buck regulator rails to reduce power dissipation in cases where there is an expectation of high VIN. If EXTSUP is unused, leave the pin open without a capacitor installed.
FBA	12	I	Feedback voltage pin for BuckA. The buck controller regulates the feedback voltage to the internal reference of 0.8 V. A suitable resistor divider network between the buck output and the feedback pin sets the desired output voltage.
FBB	27	I	Feedback voltage pin for BuckB. The buck controller regulates the feedback voltage to the internal reference of 0.8 V. A suitable resistor divider network between the buck output and the feedback pin sets the desired output voltage.
GA1	6	O	This output can drive the external high-side N-channel MOSFET for buck regulator BuckA. The output provides high peak currents to drive capacitive loads. The gate-drive reference is to a floating ground provided by PHA that has a voltage swing provided by CBA.
GA2	8	O	This output can drive the external low-side N-channel MOSFET for buck regulator BuckA. The output provides high peak currents to drive capacitive loads. VREG provides the voltage swing on this pin.
GB1	33	O	This output can drive the external high-side N-channel MOSFET for buck regulator BuckB. The output provides high peak currents to drive capacitive loads. The gate drive reference is to a floating ground provided by PHB that has a voltage swing provided by CBB.
GB2	31	O	This output can drive the external low-side N-channel MOSFET for buck regulator BuckB. The output provides high peak currents to drive capacitive loads. VREG provides the voltage swing on this pin.
GC2	4	O	This pin makes a floating output drive available to control the external P-channel MOSFET. This MOSFET can bypass the boost rectifier diode or a reverse-protection diode when the boost is not switching or if boost is disabled, and thus reduce power losses.
NC	2, 3, 18, 36	–	No connection
PGNDA	9	GND	Power ground connection to the source of the low-side N-channel MOSFETs of BuckA.
PGNDB	30	GND	Power ground connection to the source of the low-side N-channel MOSFETs of BuckB
PGA	15	O	Open-drain power-good indicator pin for BuckA. An internal power-good comparator monitors the voltage at the feedback pin and pulls this output low when the output voltage falls below 93% of the set value or if either V_IN or V_BAT drops below its respective undervoltage threshold.
PGB	24	O	Open-drain power-good indicator pin for BuckB. An internal power-good comparator monitors the voltage at the feedback pin and pulls this output low when the output voltage falls below 93% of the set value or if either V_IN or V_BAT drops below its respective undervoltage threshold..
PHA	7	O	Switching terminal of buck regulator BuckA, providing a floating ground reference for the high-side MOSFET gate-driver circuitry and used to sense current reversal in the inductor when discontinuous-mode operation is desired.
PHB	32	O	Switching terminal of buck regulator BuckB, providing a floating ground reference for the high-side MOSFET gate-driver circuitry and used to sense current reversal in the inductor when discontinuous-mode operation is desired.
RT	22	O	Connecting a resistor to ground on this pin sets the operational switching frequency of the buck and boost controllers. A short circuit to ground on this pin defaults operation to 400 kHz for the buck controllers and 200 kHz for the boost controller.
SA1	10	I	High-impedance differential-voltage inputs from the current-sense element (sense resistor or inductor DCR) for each buck controller. Choose the current-sense element to set the maximum current through the inductor based on the current-limit threshold (subject to tolerances) and considering the typical characteristics across duty cycle and V_IN. (SA1 positive node, SA2 negative node).
SA2	11	I
SB1	29	I	High-impedance differential voltage inputs from the current-sense element (sense resistor or inductor DCR) for each buck controller. Choose the current-sense element to set the maximum current through the inductor based on the current-limit threshold (subject to tolerances) and considering the typical characteristics across duty cycle and V_IN (SB1 positive node, SB2 negative node).
SB2	28	I
SSA	14	O	Soft-start or tracking input for buck controller BuckA. The buck controller regulates the FBA voltage to the lower of 0.8 V or the SSA pin voltage. An internal pullup current source of 1 µA is present at the pin, and an appropriate capacitor connected here sets the soft-start ramp interval. Alternatively, a resistor divider connected to another supply can provide a tracking input to this pin.
SSB	25	O	Soft-start or tracking input for buck controller BuckB. The buck controller regulates the FBB voltage to the lower of 0.8 V or the SSB pin voltage. An internal pullup current source of 1 µA is present at the pin, and an appropriate capacitor connected here sets the soft-start ramp interval. Alternatively, a resistor divider connected to another supply can provide a tracking input to this pin.
SYNC	20	I	If an external clock is present on this pin, the device detects it, and the internal PLL locks on to the external clock. This overrides the internal oscillator frequency. The device can synchronize to frequencies from 150 kHz to 600 kHz. A high logic level on this pin ensures forced continuous-mode operation of the buck controllers and inhibits transition to low-power mode. An open or low allows discontinuous-mode operation and entry into low-power mode at light loads. On the TPS43351-Q1, a high level enables frequency-hopping spread spectrum, whereas an open or a low level disables it.
VBAT	1	PWR	Supply pin
VIN	38	PWR	Main input pin. This is the buck controller input pin. Additionally, it powers the internal control circuits of the device.
VREG	35	O	The device requires an external capacitor on this pin to provide a regulated supply for the gate drivers of the buck and boost controllers. TI recommends capacitance on the order of 4.7 µF. The regulator obtain its power from either or EXTSUP. This pin has current-limit protection; do not use it to drive any other loads.
PowerPAD	Pad	GND	PowerPAD thermal pad is not directly connected to any leads of the package. However, it is electrically and thermally connected to the substrate, which is the ground of the device.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Voltage	Input voltage: VBAT	–0.3	60	V
Voltage (Buck function: BuckA and BuckB)	Ground: PGNDA–AGND, PGNDB–AGND	–0.3	0.3	V
	Enable inputs: ENA, ENB	–0.3	60	V
	Bootstrap inputs: CBA, CBB	–0.3	68	V
	Bootstrap inputs: CBA–PHA, CBB–PHB	–0.3	8.8	V
	Phase inputs: PHA, PHB	–0.7	60	V
	Phase inputs: PHA, PHB (for 150 ns)	–1		V
	Feedback inputs: FBA, FBB	–0.3	13	V
	Error amplifier outputs: COMPA, COMPB	–0.3	13	V
	High-side MOSFET driver: GA1–PHA, GB1–PHB	–0.3	8.8	V
	Low-side MOSFET drivers: GA2–PGNDA, GB2–PGNDB	–0.3	8.8	V
	Current-sense voltage: SA1, SA2, SB1, SB2	–0.3	13	V
	Soft start: SSA, SSB	–0.3	13	V
	Power-good output: PGA, PGB	–0.3	13	V
	Power-good delay: DLYAB	–0.3	13	V
	Switching-frequency timing resistor: RT	–0.3	13	V
	SYNC, EXTSUP	–0.3	13	V
Voltage (PMOS driver)	P-channel MOSFET driver: GC2	–0.3	60	V
Voltage (PMOS driver)	P-channel MOSFET driver: -GC2	–0.3	8.8	V
Voltage (Gate driver)	Gate-driver supply: VREG	–0.3	8.8	V
Temperature	Junction temperature: T_J	–40	150	°C
	Operating temperature: T_A	–40	125	°C
	Storage temperature: T_stg	–55	165	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to AGND, unless otherwise stated.

6.2 ESD Ratings

				VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM) AEC-Q100 Classification Level H2⁽¹⁾		±2000	V
		Charged-device model (CDM) AEC-Q100 Classification Level C2	Pins 12, 21, 22, and 27	±400
			Pins 1 and 20	±750
			All other pins	±500
		Machine model (MM)	Pins 15 and 24	±150
		Machine model (MM)	All other pins	±200

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
Buck function: BuckA and BuckB voltage	Input voltage: , VBAT	4	40	V
	Enable inputs: ENA, ENB	0	40	V
	Boot inputs: CBA, CBB	4	48	V
	Phase inputs: PHA, PHB	–0.6	40	V
	Current-sense voltage: SA1, SA2, SB1, SB2	0	11	V
	Power-good output: PGA, PGB	0	11	V
	SYNC, EXTSUP	0	9	V
Temperature	Operating temperature: T_A	–40	125	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		TPS43333-Q1	UNIT
		DAP (HTSSOP)
		38 PINS
R_θJA	Junction-to-ambient thermal resistance	27.3	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	19.6	°C/W
R_θJB	Junction-to-board thermal resistance	15.9	°C/W
ψ_JT	Junction-to-top characterization parameter	0.24	°C/W
ψ_JB	Junction-to-board characterization parameter	6.6	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	1.2	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 DC Electrical Characteristics

V_IN = 8 V to 18 V, T_J = –40°C to 150°C (unless otherwise noted)

NO.	PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
1.0	Input Supply
1.1	V_Bat	Supply voltage	After initial start-up, condition is satisfied.	4		40	V
1.2	V_IN	Input voltage required for device on initial start-up		6.5		40	V
1.2	V_IN	Buck regulator operating range after initial start-up		4		40	V
1.3	V_{IN UV}	Buck undervoltage lockout	V_IN falling. After a reset, initial start-up conditions may apply.⁽¹⁾	3.5	3.6	3.8	V
1.3	V_{IN UV}	Buck undervoltage lockout	V_INrising. After a reset, initial start-up conditions may apply.⁽¹⁾		3.8	4	V
1.5	I_{q_LPM_}	LPM quiescent current: T_A = 25°C⁽²⁾	V_IN = 13 V, BuckA: LPM, BuckB: off		30	40	µA
			V_IN = 13 V, BuckB: LPM, BuckA: off		30	40	µA
			V_IN = 13 V, BuckA, B: LPM		35	45	µA
1.6	I_{q_LPM}	LPM quiescent current: T_A = 125°C⁽²⁾	V_IN = 13 V, BuckA: LPM, BuckB: off		40	50	µA
			V_IN = 13 V, BuckB: LPM, BuckA: off		40	50	µA
			V_IN = 13 V, BuckA, B: LPM		45	55	µA
1.7	I_{q_NRM}	Quiescent current: T_A = 25°C⁽²⁾	Normal operation, SYNC = High		4.85	5.3	mA
			V_IN = 13 V, BuckA: CCM, BuckB: off		7	7.6	mA
			V_IN = 13 V, BuckB: CCM, BuckA: off
			V_IN = 13 V, BuckA, B: CCM
1.8	I_{q_NRM}	Quiescent current: T_A = 125°C⁽²⁾	Normal operation, SYNC = High		5	5.5	mA
			V_IN = 13 V, BuckA: CCM, BuckB: off		7.5	8	mA
			V_IN = 13 V, BuckB: CCM, BuckA: off
			V_IN = 13 V, BuckA, B: CCM
1.9	I_{BAT_sh}	Shutdown current	BuckA, B: off, V_BAT = 13 V		3	5	µA
2.0	Input Voltage - Overvoltage Lockout
2.1	V_OVLO	Overvoltage shutdown	V_IN rising	45	46	47	V
2.1	V_OVLO	Overvoltage shutdown	V_IN falling	43	44	45	V
2.2	OVLO_Hys	Hysteresis		1	2	3	V
2.3	OVLO_filter	Filter time			5		µs
	Gate Driver for PMOS
3.1	r_DS(on)	PMOS OFF			10	20	Ω
3.2	I_{PMOS_ON}	Gate current	V_IN = 13.5 V, V_GS = –5 V	10			mA
3.3	t_{delay_ON}	Turnon delay	C = 10 nF		5	10	µs
4.0	Buck Controllers
4.1	V_BuckA/B	Adjustable output voltage range		0.9		11	V
4.2	V_{REF, NRM}	Internal reference voltage and tolerance in normal mode	Measure FBX pin	0.792	0.8	0.808	V
4.2	V_{REF, NRM}	Internal reference voltage and tolerance in normal mode		–1%		1%
4.3	V_{REF, LPM}	Internal reference voltage and tolerance in low-power mode	Measure FBX pin	0.784	0.8	0.816	V
4.3	V_{REF, LPM}	Internal reference voltage and tolerance in low-power mode		–2%		2%
4.4	V_SENSE	V sense for forward current limit in CCM	FBx = 0.75 V (low duty cycles)	60	75	90	mV
4.5	V_SENSE	V sense for reverse current limit in CCM	FBx = 1 V	–65	–37.5	–23	mV
4.6	V_I-Foldback	V sense for output short	FBx = 0 V	17	32.5	48	mV
4.7	t_dead	Shoot-through delay, blanking time			100		ns
4.8	DC_NRM	High-side minimum on-time			100		ns
4.8	DC_NRM	Maximum duty cycle (digitally controlled)			98.75%
4.9	DC_LPM	Duty cycle LPM				80%
4.10	I_{LPM_Entry}	LPM entry threshold load current as fraction of maximum set load current	The exit threshold is specified to be always higher than entry threshold		1%	. See⁽³⁾
4.10	I_{LPM_Exit}	LPM exit threshold load current as fraction of maximum set load current	The exit threshold is specified to be always higher than entry threshold	See⁽³⁾	10%
	High-Side External NMOS Gate Drivers for Buck Controller
4.11	I_{GX1_peak}	Gate driver peak current			1.5		A
4.12	r_DS(on)	Source and sink driver	V_REG = 5.8 V, I_GX1current = 200 mA			2	Ω
	Low-Side NMOS Gate Drivers for Buck Controller
4.13	I_{GX2_peak}	Gate-driver peak current			1.5		A
4.14	r_DS(on)	Source and sink driver	V_REG = 5.8 V, I_GX2 current = 200 mA			2	Ω
	Error Amplifier (OTA) for Buck Converters
4.15	Gm_BUCK	Transconductance	COMPA, COMPB = 0.8 V, source/sink = 5 µA, test in feedback loop	0.72	1	1.35	mS
4.16	I_{PULLUP_FBx}	Pullup current at FBx pins	FBx = 0 V	50	100	200	nA
5.0	Digital Inputs: ENA, ENB, SYNC
5.1	V_IH	Higher threshold	V_IN = 13 V	1.7			V
5.2	V_IL	Lower threshold	V_IN = 13 V			0.7	V
5.3	R_{IH_SYNC}	Resistance	V_SYNC = 5 V		500		kΩ
5.5	I_{IL_ENx}	Pullup current source on ENA, ENB	V_ENx = 0 V		0.5	2	µA
6.0	Switching Parameters – Buck DC-DC Controllers
6.1	f_{SW_Buck}	Buck switching frequency	RT pin: GND	360	400	440	kHz
6.2	f_{SW_Buck}	Buck switching frequency	RT pin: 60-kΩ external resistor	360	400	440	kHz
6.3	f_{SW_adj}	Buck adjustable range with external resistor	RT pin: external resistor	150		600	kHz
6.4	f_SYNC	Buck synchronization range	External clock input	150		600	kHz
6.5	f_SS	Spread-spectrum spreading	TPS43351-Q1 only		5%
7.0	Internal Gate-Driver Supply
7.1	V_REG	Internal regulated supply	V_IN = 8 V to 18 V, EXTSUP = 0 V, SYNC = High	5.5	5.8	6.1	V
7.1	V_REG	Load regulation	I_VREG = 0 mA to 100 mA, EXTSUP = 0 V, SYNC = High		0.2%	1%
7.2	V_REG(EXTSUP)	Internal regulated supply	EXTSUP = 8.5 V	7.2	7.5	7.8	V
7.2	V_REG(EXTSUP)	Load regulation	I_EXTSUP = 0 mA to 125 mA, SYNC = High EXTSUP = 8.5 V to 13 V		0.2%	1%
7.3	V_{EXTSUP_th}	EXTSUP switch-over voltage threshold	I_VREG = 0 mA to 100 mA , EXTSUP ramping positive	4.4	4.6	4.8	V
7.4	V_EXTSUP-Hys	EXTSUP switch-over hysteresis		150		250	mV
7.5	I_REG-Limit	Current limit on VREG	EXTSUP = 0 V, normal mode as well as LPM	100		400	mA
7.6	I_{REG_EXTSUP-Limit}	Current limit on VREG when using EXTSUP	I_VREG = 0 mA to 100 mA, EXTSUP = 8.5 V, SYNC = High	125		400	mA
8.0	Soft Start
8.1	I_SSx	Soft-start source current	SSA and SSB = 0 V	0.75	1	1.25	µA
9.0	Oscillator (RT)
9.1	V_RT	Oscillator reference voltage			1.2		V
10.0	Power-Good / Delay
10.1	PG_pullup	Pullup for A and B to Sx2			50		kΩ
10.2	PG_th1	Power-good threshold	FBx falling	–5%	–7%	–9%
10.3	PG_hys	Hysteresis			2%
10.4	PG_drop	Voltage drop	I_PGA = 5 mA			450	mV
10.5			I_PGA = 1 mA			100	mV
10.6	PG_leak	Leakage	VSx2 = VPGx = 13 V			1	µA
10.7	t_deglitch	Power-good deglitch time		2		16	µs
10.8	t_delay	Reset delay	External capacitor = 1 nF V_BuckX < PG_th1		1		ms
10.9	t_{delay_fix}	Fixed reset delay	No external capacitor, pin open		20	50	µs
10.10	I_OH	Activate current source (current to charge external capacitor)		30	40	50	µA
10.11	I_IL	Activate current sink (current to discharge external capacitor)		30	40	50	µA
11.0	Overtemperature Protection
11.1	T_shutdown	Junction temperature shutdown threshold		150	165		°C
11.2	T_hys	Junction temperature hysteresis			15		°C