SLVSAU0G May   2011  – December 2015 TPD4S014

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics, EN, ACK, D+, D-, ID Pins
    6. 6.6 Electrical Characteristics OVP Circuits
    7. 6.7 Supply Current Consumption
    8. 6.8 Thermal Shutdown Feature
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Voltage Protection at VBUS up to 28 V DC
      2. 7.3.2 Low RON nFET Switch
      3. 7.3.3 ESD Performance D+/D-/ID/VBUS Pins
      4. 7.3.4 Overvoltage and Undervoltage Lockout Features
      5. 7.3.5 Capacitance TVS ESD Clamp for USB2.0 Hi-Speed Data Rate
      6. 7.3.6 Start-up Delay
      7. 7.3.7 OVP Glitch Immunity
      8. 7.3.8 Integrated Input Enable and Status Output Signal
      9. 7.3.9 Thermal Shutdown
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 For Non-OTG USB Systems
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 For OTG USB Systems
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

DSQ Package
10-Pin WSON
Top Side/See-Through View
TPD4S014 po_lvsau0.gif

Pin Functions

PIN TYPE DESCRIPTION
NAME NO.
VBUSOUT 1, 2 Power Output Connect to PCB internal PCB plane
EN 3 IO Enable Active-Low Input. Drive EN low to enable the switch. Drive EN high to disable the switch.
ACK 4 I Open-Drain Adapter-Voltage Indicator Output. ACK is driven low after the VIN voltage is stable between UVLO and OVLO for 17 ms (typ). Connect a pullup resistor from ACK to the logic I/O voltage of the host system.
ID 5 IO ESD-protected line
D– 6 IO ESD-protected line
D+ 7 IO ESD-protected line
GND 8 Ground Ground
VBUS 9, 10 USB Input Power Connector Side of VBUS
Central PAD Central PAD Heat Sink Electrically disconnected. Use as heat sink. Connect to GND plane via large PCB PAD