The TPS54623 in thermally enhanced VQFN package is a full featured 17-V, 6-A synchronous step-down converter which is optimized for small designs through high efficiency and integrating the high-side and low-side MOSFETs. Further space savings are achieved through current mode control, which reduces component count, and by selecting a high switching frequency, reducing the inductor's footprint.
The output voltage start-up ramp is controlled by the SS/TR pin, which allows operation as either a stand alone power supply or in tracking situations. Power sequencing is also possible by correctly configuring the enable and the open drain power good pins.
Cycle-by-cycle current limiting on the high-side FET protects the device in overload situations and is enhanced by a low-side sourcing current limit which prevents current runaway. There is also a low-side sinking current limit that turns off the low-side MOSFET to prevent excessive reverse current. Hiccup protection will be triggered if the overcurrent condition has persisted for longer than the preset time. Thermal hiccup protection disables the device when the die temperature exceeds the thermal shutdown temperature and enables the part again after the built-in thermal shutdown hiccup time. The TPS54623 operates at continuous current mode (CCM) at higher load conditions while skipping pulses to boost the efficiency at light loads.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TPS54623 | VQFN (14) | 3.50 mm × 3.50 mm |
Changes from B Revision (January 2017) to C Revision
Changes from A Revision (March 2016) to B Revision
Changes from * Revision (September 2011) to A Revision
MIN | MAX | UNIT | ||
---|---|---|---|---|
Input voltage | VIN | –0.3 | 20 | V |
PVIN | –0.3 | 20 | ||
EN | –0.3 | 6 | ||
BOOT | –0.3 | 27 | ||
VSENSE | –0.3 | 3 | ||
COMP | –0.3 | 3 | ||
PWRGD | –0.3 | 6 | ||
SS/TR | –0.3 | 3 | ||
RT/CLK | –0.3 | 6 | ||
Output voltage | BOOT-PH | 0 | 7.5 | V |
PH | –1 | 20 | ||
PH (10-ns transient) | –3 | 20 | ||
Vdiff (GND to exposed thermal pad) | –0.2 | 0.2 | V | |
Source current | RT/CLK | ±100 | µA | |
PH | Current limit | A | ||
Sink current | PH | Current limit | A | |
PVIN | Current limit | A | ||
COMP | ±200 | µA | ||
PWRGD | –0.1 | 5 | mA | |
Operating junction temperature, TJ | –40 | 150 | °C | |
Storage temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
VVIN | Input voltage | 4.5 | 17 | V | |
VPVIN | Input voltage | 1.7 | 17 | V | |
IOUT | Output current | 0 | 6 | A | |
TJ | Operating junction temperature | –40 | 150 | °C |
THERMAL METRIC(1)(2) | TPS54623 | UNIT | ||
---|---|---|---|---|
RHL (VQFN) | ||||
14 PINS | ||||
RθJA | Junction-to-ambient | Thermal resistance | 40.1 | °C/W |
Test board(3) | 32 | |||
RθJC(top) | Junction-to-case (top) thermal resistance | 34.4 | °C/W | |
RθJB | Junction-to-board thermal resistance | 11.4 | °C/W | |
ψJT | Junction-to-top characterization parameter | 0.5 | °C/W | |
ψJB | Junction-to-board characterization parameter | 11.4 | °C/W | |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 1.8 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
SUPPLY VOLTAGE (VIN AND PVIN PINS) | ||||||
PVIN operating input voltage | 1.6 | 17 | V | |||
VIN operating input voltage | 4.5 | 17 | V | |||
VIN internal UVLO threshold | VIN rising | 4.0 | 4.5 | V | ||
VIN internal UVLO hysteresis | 150 | mV | ||||
VIN shutdown supply Current | EN = 0 V | 2 | 5 | μA | ||
VIN operating – non switching supply current | VSENSE = 810 mV | 250 | 500 | μA | ||
ENABLE AND UVLO (EN PIN) | ||||||
Enable threshold | Rising | 1.21 | 1.26 | V | ||
Enable threshold | Falling | 1.10 | 1.17 | V | ||
Input current | EN = 1.1 V | 1.15 | μA | |||
Hysteresis current | EN = 1.3 V | 3.3 | μA | |||
VOLTAGE REFERENCE | ||||||
Voltage reference | 0 A ≤ IOUT ≤ 6 A | 0.594 | 0.6 | 0.606 | V | |
MOSFET | ||||||
High-side switch resistance | BOOT-PH = 3 V | 32 | 60 | mΩ | ||
High-side switch resistance(1) | BOOT-PH = 6 V | 26 | 40 | mΩ | ||
Low-side switch resistance(1) | VIN = 12 V | 19 | 30 | mΩ | ||
ERROR AMPLIFIER | ||||||
Error amplifier Transconductance (gm) | –2 μA < ICOMP < 2 μA, V(COMP) = 1 V | 1300 | μMhos | |||
Error amplifier dc gain | VSENSE = 0.6 V | 1000 | 3100 | V/V | ||
Error amplifier source/sink | V(COMP) = 1 V, 100 mV input overdrive | ±110 | μA | |||
Start switching peak current threshold | 1 | A | ||||
COMP to Iswitch gm | 16 | A/V | ||||
CURRENT LIMIT | ||||||
High-side switch current limit threshold | 8 | 11 | 14 | A | ||
Low-side switch sourcing current limit | 6.5 | 10 | 15 | A | ||
Low-side switch sinking current limit | 200 | 600 | mA | |||
Hiccup wait time | 512 | Cycles | ||||
Hiccup time before re-start | 16384 | Cycles | ||||
THERMAL SHUTDOWN | ||||||
Thermal shutdown | 160 | 175 | °C | |||
Thermal shutdown hysteresis | 10 | °C | ||||
Thermal shutdown hiccup time | 16384 | Cycles | ||||
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN) | ||||||
Minimum switching frequency | RRT = 240 kΩ (1%) | 160 | 200 | 240 | kHz | |
Switching frequency | RRT = 100 kΩ (1%) | 400 | 480 | 560 | kHz | |
Maximum switching frequency | RRT = 29 kΩ (1%) | 1440 | 1600 | 1760 | kHz | |
Minimum pulse width | 20 | ns | ||||
RT/CLK high threshold | 2 | V | ||||
RT/CLK low threshold | 0.8 | V | ||||
RT/CLK falling edge to PH rising edge delay | Measure at 500 kHz with RT resistor in series | 66 | ns | |||
Switching frequency range (RT mode set point and PLL mode) | 200 | 1600 | kHz | |||
PH (PH PIN) | ||||||
Minimum on-time | Measured at 90% to 90% of VIN, 25°C, IPH = 2 A | 94 | 145 | ns | ||
Minimum off-time | BOOT-PH ≥ 3 V | 0 | ns | |||
BOOT (BOOT PIN) | ||||||
BOOT-PH UVLO | 2.1 | 3 | V | |||
SLOW START AND TRACKING (SS/TR PIN) | ||||||
SS charge current | 2.3 | μA | ||||
SS/TR to VSENSE matching | V(SS/TR) = 0.4 V | 20 | 60 | mV | ||
POWER GOOD (PWRGD PIN) | ||||||
VSENSE threshold | VSENSE falling (Fault) | 92% | Vref | |||
VSENSE rising (good) | 94% | Vref | ||||
VSENSE rising (Fault) | 106% | Vref | ||||
VSENSE falling (Good) | 104% | Vref | ||||
Output high leakage | VSENSE = Vref, V(PWRGD) = 5.5 V | 30 | 100 | nA | ||
Output low | I(PWRGD) = 2 mA | 0.3 | V | |||
Minimum VIN for valid output | V(PWRGD) < 0.5 V at 100 μA | 0.6 | 1 | V | ||
Minimum SS/TR voltage for PWRGD | 1.4 | V |
The device is a 17-V, 6-A, synchronous step-down (buck) converter with two integrated n-channel MOSFETs. To improve performance during line and load transients the device implements a constant frequency, peak current mode control which also simplifies external frequency compensation. The wide switching frequency of 200 kHz to 1600 kHz allows for efficiency and size optimization when selecting the output filter components. The switching frequency is adjusted using a resistor to ground on the RT/CLK pin. The device also has an internal phase lock loop (PLL) controlled by the RT/CLK pin that can be used to synchronize the switching cycle to the falling edge of an external system clock.
The device has been designed for safe monotonic start-up into pre-biased loads. The default start up is when VIN is typically 4 V. The EN pin has an internal pullup current source that can be used to adjust the input voltage under voltage lockout (UVLO) with two external resistors. In addition, the EN pin can be floating for the device to operate with the internal pullup current. The total operating current for the device is approximately 600 μA when not switching and under no load. When the device is disabled, the supply current is typically less than 2 μA.
The integrated MOSFETs allow for high efficiency power supply designs with continuous output currents up to 6 A. The MOSFETs have been sized to optimize efficiency for lower duty cycle applications.
The device reduces the external component count by integrating the boot recharge circuit. The bias voltage for the integrated high-side MOSFET is supplied by a capacitor between the BOOT and PH pins. The boot capacitor voltage is monitored by a BOOT to PH UVLO (BOOT-PH UVLO) circuit allowing PH pin to be pulled low to recharge the boot capacitor. The device can operate at 100% duty cycle as long as the boot capacitor voltage is higher than the preset BOOT-PH UVLO threshold which is typically 2.1 V. The output voltage can be stepped down to as low as the 0.6 V voltage reference (Vref).
The device has a power good comparator (PWRGD) with hysteresis which monitors the output voltage through the VSENSE pin. The PWRGD pin is an open drain MOSFET which is pulled low when the VSENSE pin voltage is less than 92% or greater than 106% of the reference voltage Vref and asserts high when the VSENSE pin voltage is 94% to 104% of the Vref.
The SS/TR (slow start/tracking) pin is used to minimize inrush currents or provide power supply sequencing during power up. A small value capacitor or resistor divider should be coupled to the pin for slow start or critical power supply sequencing requirements.
The device is protected from output overvoltage, overload and thermal fault conditions. The device minimizes excessive output overvoltage transients by taking advantage of the overvoltage circuit power good comparator. When the overvoltage comparator is activated, the high-side MOSFET is turned off and prevented from turning on until the VSENSE pin voltage is lower than 104% of the Vref. The device implements both high-side MOSFET overload protection and bidirectional low-side MOSFET overload protections which help control the inductor current and avoid current runaway. The device also shuts down if the junction temperature is higher than thermal shutdown trip point. The device is restarted under control of the slow start circuit automatically after the built-in thermal shutdown hiccup time.
The TPS54623 monitors the peak switch current of the high-side MOSFET. Once the peak switch current is lower than typically 1 A, the device stops switching to boost the efficiency until the peak switch current is higher than typically 1 A again.
The device allows for a variety of applications by using the VIN and PVIN pins together or separately. The VIN pin voltage supplies the internal control circuits of the device. The PVIN pin voltage provides the input voltage to the power converter system.
If tied together, the input voltage for VIN and PVIN can range from 4.5 V to 17 V. If using the VIN separately from PVIN, the VIN pin must be between 4.5 V and 17 V, and the PVIN pin can range from as low as 1.6 V to 17 V. A voltage divider connected to the EN pin can adjust the either input voltage UVLO appropriately. Adjusting the input voltage UVLO on the PVIN pin helps to provide consistent power up behavior.
The voltage reference system produces a precise ±1% voltage reference over temperature by scaling the output of a temperature stable bandgap circuit.
The output voltage is set with a resistor divider from the output (VOUT) to the VSENSE pin. It is recommended to use 1% tolerance or better divider resistors. Referring to the application schematic of Figure 31, start with a 10 kΩ for R6 and use Equation 1 to calculate R5. To improve efficiency at light loads consider using larger value resistors. If the values are too high the regulator is more susceptible to noise and voltage errors from the VSENSE input current are noticeable.
where
The minimum output voltage and maximum output voltage can be limited by the minimum on time of the high-side MOSFET and bootstrap voltage (BOOT-PH voltage) respectively. More discussions are located in Minimum Output Voltage and Bootstrap Voltage (BOOT) and Low Dropout Operation.
The device has been designed to prevent the low-side MOSFET from discharging a pre-biased output. During monotonic pre-biased startup, the low-side MOSFET is not allowed to sink current until the SS/TR pin voltage is higher than 1.4 V.
The device uses a transconductance error amplifier. The error amplifier compares the VSENSE pin voltage to the lower of the SS/TR pin voltage or the internal 0.6 V voltage reference. The transconductance of the error amplifier is 1300 μA/V during normal operation. The frequency compensation network is connected between the COMP pin and ground.
The device adds a compensating ramp to the switch current signal. This slope compensation prevents sub-harmonic oscillations. The available peak inductor current remains constant over the full duty cycle range.
The EN pin provides electrical on/off control of the device. Once the EN pin voltage exceeds the threshold voltage, the device starts operation. If the EN pin voltage is pulled below the threshold voltage, the regulator stops switching and enters low Iq state.
The EN pin has an internal pullup current source, allowing the user to float the EN pin for enabling the device. If an application requires controlling the EN pin, use open drain or open collector output logic to interface with the pin.
The device implements internal UVLO circuitry on the VIN pin. The device is disabled when the VIN pin voltage falls below the internal VIN UVLO threshold. The internal VIN UVLO threshold has a hysteresis of 150 mV.
If an application requires either a higher UVLO threshold on the VIN pin or a secondary UVLO on the PVIN, in split rail applications, then the EN pin can be configured as shown in Figure 17, Figure 18 and Figure 19. When using the external UVLO function it is recommended to set the hysteresis to be greater than 500 mV.
The EN pin has a small pullup current Ip which sets the default state of the pin to enable when no external components are connected. The pullup current is also used to control the voltage hysteresis for the UVLO function since it increases by Ih once the EN pin crosses the enable threshold. The UVLO thresholds can be calculated using Equation 2 and Equation 3.
where
The device uses the lower voltage of the internal voltage reference or the SS/TR pin voltage as the reference voltage and regulates the output accordingly. A capacitor on the SS/TR pin to ground implements a slow start time. The device has an internal pullup current source of 2.3 μA that charges the external slow start capacitor. The calculations for the slow start time (Tss, 10% to 90%) and slow start capacitor (Css) are shown in Equation 4. The voltage reference (Vref) is 0.6 V and the slow start charge current (Iss) is 2.3 μA.
When the input UVLO is triggered, the EN pin is pulled below 1.21 V, or a thermal shutdown event occurs the device stops switching and enters low current operation. At the subsequent power up, when the shutdown condition is removed, the device does not start switching until it has discharged its SS/TR pin to ground ensuring proper soft start behavior.
The PWRGD pin is an open drain output. Once the VSENSE pin is between 94% and 104% of the internal voltage reference the PWRGD pin pull-down is de-asserted and the pin floats. It is recommended to use a pullup resistor between the values of 10 kΩ and 100 kΩ to a voltage source that is 5.5 V or less. The PWRGD is in a defined state once the VIN input voltage is greater than 1 V but with reduced current sinking capability. The PWRGD achieves full current sinking capability once the VIN input voltage is above 4.5 V.
The PWRGD pin is pulled low when VSENSE is lower than 92% or greater than 106% of the nominal internal reference voltage. Also, the PWRGD is pulled low, if the input UVLO or thermal shutdown are asserted, the EN pin is pulled low or the SS/TR pin is below 1.4 V.
The device has an integrated boot regulator, and requires a small ceramic capacitor between the BOOT and PH pins to provide the gate drive voltage for the high-side MOSFET. The boot capacitor is charged when the BOOT pin voltage is less than VIN and BOOT-PH voltage is below regulation. The value of this ceramic capacitor should be 0.1 μF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V or higher is recommended because of the stable characteristics over temperature and voltage.
To improve drop out, the device is designed to operate at 100% duty cycle as long as the BOOT to PH pin voltage is greater than the BOOT-PH UVLO threshold which is typically 2.1 V. When the voltage between BOOT and PH drops below the BOOT-PH UVLO threshold the high-side MOSFET is turned off and the low-side MOSFET is turned on allowing the boot capacitor to be recharged. In applications with split input voltage rails 100% duty cycle operation can be achieved as long as (VIN – PVIN) > 4 V.
Many of the common power supply sequencing methods can be implemented using the SS/TR, EN and PWRGD pins.
The sequential method is illustrated in Figure 20 using two TPS54623 devices. The power good of the first device is coupled to the EN pin of the second device, which enables the second power supply once the primary supply reaches regulation.
Figure 21 shows the method implementing ratio-metric sequencing by connecting the SS/TR pins of two devices together. The regulator outputs ramp up and reach regulation at the same time. When calculating the slow start time the pullup current source must be doubled in Equation 4.
Ratio-metric and simultaneous power supply sequencing can be implemented by connecting the resistor network of R1 and R2 shown in Figure 22 to the output of the power supply that needs to be tracked or another voltage reference source. Using Equation 5 and Equation 6, the tracking resistors can be calculated to initiate the Vout2 slightly before, after or at the same time as Vout1. Equation 7 is the voltage difference between Vout1 and Vout2.
To design a ratio-metric start up in which the Vout2 voltage is slightly greater than the Vout1 voltage when Vout2 reaches regulation, use a negative number in Equation 5 and Equation 6 for deltaV. Equation 7 results in a positive number for applications where the Vout2 is slightly lower than Vout1 when Vout2 regulation is achieved. .
The deltaV variable is zero volt for simultaneous sequencing. To minimize the effect of the inherent SS/TR to VSENSE offset (Vssoffset, 29 xmV) in the slow start circuit and the offset created by the pullup current source (Iss, 2.3 μA) and tracking resistors, the Vssoffset and Iss are included as variables in the equations.
To ensure proper operation of the device, the calculated R1 value from Equation 5 must be greater than the value calculated in Equation 8.
There are two final considerations when using a resistor divider to the SS/TR pin for simultaneous start-up. First, as described in Power Good (PWRGD), for the PWRGD output to be active the SS/TR voltage must be above 1.4 V. The external divider may prevent the SS/TR voltage from charging above the threshold. For the SS/TR pin to charge above the threshold, an external MOSFET may be needed to disconnect the resistor divider or modify the resistor divider ratio after start-up is complete. The PWRGD pin of the VOUT(1) converter could be used to turn on or turn off the external MOSFET. Second, a pre-bias on VOUT(1) may prevent VOUT(2) from turning on. When the TPS54623 is enabled, an internal 700-Ω MOSFET at the SS/TR pin turns on to discharge the SS/TR voltage as described in Slow Start (SS/TR). The SS/TR pin voltage must discharge below 20 mV before the TPS54623 starts up. If the upper resistor at the SS/TR pin is too small, the SS/TR pin does not discharge below the threshold, and VOUT(2) does not ramp up. The upper resistor in the SS/TR divider may need to be increased to allow the SS/TR pin to discharge below the threshold.
The device incorporates an output overvoltage protection (OVP) circuit to minimize output voltage overshoot. For example, when the power supply output is overloaded the error amplifier compares the actual output voltage to the internal reference voltage. If the VSENSE pin voltage is lower than the internal reference voltage for a considerable time, the output of the error amplifier demands maximum output current. Once the condition is removed, the regulator output rises and the error amplifier output transitions to the steady state voltage. In some applications with small output capacitance, the power supply output voltage can respond faster than the error amplifier. This leads to the possibility of an output overshoot. The OVP feature minimizes the overshoot by comparing the VSENSE pin voltage to the OVP threshold. If the VSENSE pin voltage is greater than the OVP threshold the high-side MOSFET is turned off preventing current from flowing to the output and minimizing output overshoot. When the VSENSE voltage drops lower than the OVP threshold, the high-side MOSFET is allowed to turn on at the next clock cycle.
The device is protected from overcurrent conditions by cycle-by-cycle current limiting on both the high-side MOSFET and the low-side MOSFET.
The device implements current mode control which uses the COMP pin voltage to control the turnoff of the high-side MOSFET and the turnon of the low-side MOSFET on a cycle by cycle basis. Each cycle the switch current and the current reference generated by the COMP pin voltage are compared, when the peak switch current intersects the current reference the high-side switch is turned off.
While the low-side MOSFET is turned on its conduction current is monitored by the internal circuitry. During normal operation the low-side MOSFET sources current to the load. At the end of every clock cycle, the low-side MOSFET sourcing current is compared to the internally set low-side sourcing current limit. If the low-side sourcing current is exceeded the high-side MOSFET is not turned on and the low-side MOSFET stays on for the next cycle. The high-side MOSFET is turned on again when the low-side current is below the low-side sourcing current limit at the start of a cycle.
The low-side MOSFET may also sink current from the load. If the low-side sinking current limit is exceeded the low-side MOSFET is turned off immediately for the rest of that clock cycle. In this scenario both MOSFETs are off until the start of the next cycle.
Furthermore, if an output overload condition (as measured by the COMP pin voltage) has lasted for more than the hiccup wait time which is programmed for 512 switching cycles, the device shuts down itself and restart after the hiccup time of 16384 cycles. The hiccup mode helps to reduce the device power dissipation under severe overcurrent conditions.
The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds 175°C typically. Once the junction temperature drops below 165°C typically, the internal thermal hiccup timer will start to count. The device reinitiates the power up sequence after the built-in thermal shutdown hiccup time (16384 cycles) is over.
Figure 23 shows an equivalent model for the device control loop which can be modeled in a circuit simulation program to check frequency response and transient responses. The error amplifier is a transconductance amplifier with a gm of 1300μA/V. The error amplifier can be modeled using an ideal voltage controlled current source. The resistor Roea (2.38 MΩ) and capacitor Coea (20.7 pF) model the open loop gain and frequency response of the error amplifier. The 1-mV ac voltage source between the nodes a and b effectively breaks the control loop for the frequency response measurements. Plotting a/c and c/b show the small signal responses of the power stage and frequency compensation respectively. Plotting a/b shows the small signal response of the overall loop. The dynamic loop response can be checked by replacing the RL with a current source with the appropriate load step amplitude and step rate in a time domain analysis.
Figure 24 is a simple small signal model that can be used to understand how to design the frequency compensation. The device power stage can be approximated to a voltage controlled current source (duty cycle modulator) supplying current to the output capacitor and load resistor. The control to output transfer function is shown in Equation 9 and consists of a dc gain, one dominant pole and one ESR zero. The quotient of the change in switch current and the change in COMP pin voltage (node c in Figure 23) is the power stage transconductance (gmps) which is 16 A/V for the device. The DC gain of the power stage is the product of gmps and the load resistance RL) as shown in Equation 10 with resistive loads. As the load current increases, the DC gain decreases. This variation with load may seem problematic at first glance, but fortunately the dominant pole moves with load current (see Equation 11). The combined effect is highlighted by the dashed line in Figure 25. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover frequency the same for the varying load conditions which makes it easier to design the frequency compensation.
where
The device uses a transconductance amplifier for the error amplifier and readily supports two of the commonly used Type II compensation circuits and a Type III frequency compensation circuit, as shown in Figure 26. In Type 2A, one additional high frequency pole, C6, is added to attenuate high frequency noise. In Type III, one additional capacitor, C11, is added to provide a phase boost at the crossover frequency. See Designing Type III Compensation for Current Mode Step-Down Converters (for a complete explanation of Type III compensation.
The design guidelines below are provided for advanced users who prefer to compensate using the general method. The below equations only apply to designs whose ESR zero is above the bandwidth of the control loop. This is usually true with ceramic output capacitors. See Typical Application for a step-by-step design procedure using higher ESR output capacitors with lower ESR zero frequencies.
The general design guidelines for device loop compensation are as follows:
where
The device uses a adjustable fixed frequency, peak current mode control. The output voltage is compared through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives the COMP pin. An internal oscillator initiates the turn on of the high-side power switch. The error amplifier output is converted into a current reference which compares to the high-side power switch current. When the power switch current reaches current reference generated by the COMP voltage level the high-side power switch is turned off and the low-side power switch is turned on.
As a synchronous buck converter, the device normally works in CCM (Continuous Conduction Mode) under load conditions where the minimum inductor valley current is higher than 0 A.
The TPS54623 operates in pulse skip mode (see Figure 28) at light load currents to improve efficiency by reducing switching and gate drive losses. The TPS54623 is designed so that if the output voltage is within regulation and the peak switch current at the end of any switching cycle is below the pulse skipping current threshold, the device enters pulse skip mode. This current threshold is the current level corresponding to a nominal COMP voltage of 250 mV.
When in pulse skip mode, the COMP pin voltage is clamped and the high side MOSFET is inhibited. Further decreases in load current or in output voltage can not drive the COMP pin below this clamp voltage level.
Since the device is not switching, the output voltage begins to decay. As the voltage control loop compensates for the falling output voltage, the COMP pin voltage begins to rise. At this time, the high side MOSFET is enabled and a switching pulse initiates on the next switching cycle. The peak current is set by the COMP pin voltage. The output voltage re-charges the regulated value, then the peak switch current starts to decrease, and eventually falls below the pulse skip mode threshold at which time the device again enters pulse skip mode.
The RT/CLK pin can be used to set the switching frequency of the device in two modes.
In RT mode, a resistor (RT resistor) is connected between the RT/CLK pin and GND. The switching frequency of the device is adjustable from 200 kHz to 1600 kHz by placing a maximum of 240 kΩ and minimum of 29 kΩ respectively. In CLK mode, an external clock is connected directly to the RT/CLK pin. The device is synchronized to the external clock frequency with PLL.
The CLK mode overrides the RT mode. The device is able to detect the proper mode automatically and switch from the RT mode to CLK mode.
To determine the RT resistance for a given switching frequency, use Equation 17 or the curve in Figure 29. To reduce the solution size one would set the switching frequency as high as possible, but tradeoffs of the supply efficiency and minimum controllable on time should be considered.
An internal phase locked loop (PLL) has been implemented to allow synchronization between 200 kHz and 1600 kHz, and to easily switch from RT mode to CLK mode.
To implement the synchronization feature, connect a square wave clock signal to the RT/CLK pin with a duty cycle between 20% to 80%. The clock signal amplitude must transition lower than 0.8 V and higher than 2 V. The start of the switching cycle is synchronized to the falling edge of RT/CLK pin.
In applications where both RT mode and CLK mode are needed, the device can be configured as shown in Figure 30. Before the external clock is present, the device works in RT mode and the switching frequency is set by RT resistor. When the external clock is present, the CLK mode overrides the RT mode. The first time the SYNC pin is pulled above the RT/CLK high threshold (2 V), the device switches from the RT mode to the CLK mode and the RT/CLK pin becomes high impedance as the PLL starts to lock onto the frequency of the external clock. It is not recommended to switch from the CLK mode back to the RT mode because the internal switching frequency drops to 100 kHz first before returning to the switching frequency set by RT resistor.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
In applications where fast transient responses are important, Type III frequency compensation can be used instead of the traditional Type II frequency compensation.
For more information about Type II and Type III frequency compensation circuits, see Designing Type III Compensation for Current Mode Step-Down Converters (SLVA352) and Design Calculator (SLVC219).
This example details the design of a high frequency switching regulator design using ceramic output capacitors. A few parameters must be known in order to start the design process. These parameters are typically determined at the system level. For this example, start with the parameters in Table 1.
PARAMETER | VALUE |
---|---|
Output voltage | 3.3 V |
Output current | 6 A |
Transient response 1-A load step | ΔVOUT = 5 % |
Input voltage | 12 V nominal, 8 V to 17 V |
Output voltage ripple | 33 mV p-p |
Start input voltage (rising VIN) | 6.528 V |
Stop input voltage (falling VIN) | 6.19 V |
Switching frequency | 480 kHz |
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The first step is to decide on a switching frequency for the regulator. There is a trade off between higher and lower switching frequencies. Higher switching frequencies may produce smaller a solution size using lower valued inductors and smaller output capacitors compared to a power supply that switches at a lower frequency. However, the higher switching frequency causes extra switching losses, which hurt the converter’s efficiency and thermal performance. In this design, a moderate switching frequency of 480 kHz is selected to achieve both a small solution size and a high efficiency operation.
To calculate the value of the output inductor, use Equation 18. KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current. The inductor ripple current is filtered by the output capacitor. Therefore, choosing high inductor ripple currents impact the selection of the output capacitor since the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. In general, the inductor ripple value is at the discretion of the designer; however, KIND is normally from 0.1 to 0.3 for the majority of applications.
For this design example, use KIND = 0.3 and the inductor value is calculated to be 3.08 µH. For this design, a nearest standard value was chosen: 3.3 µH. For the output filter inductor, it is important that the RMS current and saturation current ratings not be exceeded. The RMS and peak inductor current can be found from Equation 20 and Equation 21.
For this design, the RMS inductor current is 6.02 A and the peak inductor current is 6.84 A. The chosen inductor is a Coilcraft MSS1048 series 3.3 µH. It has a saturation current rating of 7.38 A and a RMS current rating of 7.22 A.
The current flowing through the inductor is the inductor ripple current plus the output current. During power up, faults or transient load conditions, the inductor current can increase above the calculated peak inductor current level calculated above. In transient conditions, the inductor current can increase up to the switch current limit of the device. For this reason, the most conservative approach is to specify an inductor with a saturation current rating equal to or greater than the switch current limit rather than the peak inductor current.
There are three primary considerations for selecting the value of the output capacitor. The output capacitor determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in load current. The output capacitance needs to be selected based on the more stringent of these three criteria.
The desired response to a large change in the load current is the first criteria. The output capacitor needs to supply the load with current when the regulator can not. This situation would occur if there are desired hold-up times for the regulator where the output capacitor must hold the output voltage above a certain level for a specified amount of time after the input power is removed. The regulator is also temporarily not able to supply sufficient output current if there is a large, fast increase in the current needs of the load such as a transition from no load to full load. The regulator usually needs two or more clock cycles for the control loop to see the change in load current and output voltage and adjust the duty cycle to react to the change. The output capacitor must be sized to supply the extra current to the load until the control loop responds to the load change. The output capacitance must be large enough to supply the difference in current for 2 clock cycles while only allowing a tolerable amount of droop in the output voltage. Equation 22 shows the minimum output capacitance necessary to accomplish this.
Where ΔIout is the change in output current, fsw is the regulators switching frequency and ΔVout is the allowable change in the output voltage. For this example, the transient load response is specified as a 5% change in Vout for a load step of 1 A. For this example, ΔIout = 3.0 A and ΔVout = 0.05 × 3.3 = 0.165 V. Using these numbers gives a minimum capacitance of 75.8 μF. This value does not take the ESR of the output capacitor into account in the output voltage change. For ceramic capacitors, the ESR is usually small enough to ignore in this calculation.
Equation 23 calculates the minimum output capacitance needed to meet the output voltage ripple specification. Where fsw is the switching frequency, Vripple is the maximum allowable output voltage ripple, and Iripple is the inductor ripple current. In this case, the maximum output voltage ripple is 33 mV. Under this requirement, Equation 23 yields 13.2 µF.
Equation 24 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple specification. Equation 24 indicates the ESR should be less than 19.7 mΩ. In this case, the ceramic caps’ ESR is much smaller than 19.7 mΩ.
Additional capacitance de-ratings for aging, temperature and DC bias should be factored in which increases this minimum value. For this example, a 100-μF 6.3-V X5R ceramic capacitor with 3 mΩ of ESR is be used. Capacitors generally have limits to the amount of ripple current they can handle without failing or producing excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor data sheets specify the root mean square (RMS) value of the maximum ripple current. Equation 25 can be used to calculate the RMS ripple current the output capacitor needs to support. For this application, Equation 25 yields 485 mA.
The TPS54623 requires a high quality ceramic, type X5R or X7R, input decoupling capacitor of at least 4.7 µF of effective capacitance on the PVIN input voltage pins and 4.7 µF on the Vin input voltage pin. In some applications additional bulk capacitance may also be required for the PVIN input. The effective capacitance includes any DC bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple current rating greater than the maximum input current ripple of the TPS54623. The input ripple current can be calculated using Equation 26.
The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors because they have a high capacitance to volume ratio and are fairly stable over temperature. The output capacitor must also be selected with the DC bias taken into account. The capacitance value of a capacitor decreases as the DC bias across a capacitor increases. For this example design, a ceramic capacitor with at least a 25 V voltage rating is required to support the maximum input voltage. For this example, one 10 μF and one 4.7 µF 25 V capacitors in parallel have been selected as the VIN and PVIN inputs are tied together so the TPS54623 may operate from a single supply. The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be calculated using Equation 27. Using the design example values, Ioutmax = 6 A, Cin = 14.7 μF, fsw = 480 kHz, yields an input voltage ripple of 213 mV and a RMS input ripple current of 2.95 A.
The slow start capacitor determines the minimum amount of time it takes for the output voltage to reach its nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This is also used if the output capacitance is very large and would require large amounts of current to quickly charge the capacitor to the output voltage level. The large currents necessary to charge the capacitor may make the TPS54623 reach the current limit or excessive current draw from the input power supply may cause the input voltage rail to sag. Limiting the output voltage slew rate solves both of these problems. The soft start capacitor value can be calculated using Equation 28. For the example circuit, the soft start time is not too critical since the output capacitor value is 100 μF which does not require much current to charge to 3.3 V. The example circuit has the soft start time set to an arbitrary value of 6 ms which requires a 22 nF capacitor. In TPS54623, Iss is 2.3 uA and Vref is 0.6 V.
A 0.1-µF ceramic capacitor must be connected between the BOOT to PH pin for proper operation. It is recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have 10 V or higher voltage rating.
The Undervoltage Lockout (UVLO) can be adjusted using the external voltage divider network of R3 and R4. R3 is connected between VIN and the EN pin of the TPS54623 and R4 is connected between EN and GND . The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down or brown outs when the input voltage is falling. For the example design, the supply should turn on and start switching once the input voltage increases above 6.528 V (UVLO start or enable). After the regulator starts switching, it should continue to do so until the input voltage falls below 6.190 V (UVLO stop or disable). Equation 2 and Equation 3 can be used to calculate the values for the upper and lower resistor values. For the stop voltages specified the nearest standard resistor value for R3 is 35.7 kΩ and for R4 is 8.06 kΩ.
The resistor divider network R5 and R6 is used to set the output voltage. For the example design, 10 kΩ was selected for R5. Using Equation 29, R6 is calculated as 2.22 kΩ. The nearest standard 1% resistor is 2.21 kΩ.
Due to the internal design of the TPS54623, there is a minimum output voltage limit for any given input voltage. The output voltage can never be lower than the internal voltage reference of 0.6 V. Above 0.6 V, the output voltage may be limited by the minimum controllable on time. The minimum output voltage in this case is given by Equation 30.
where
There are several industry techniques used to compensate DC/DC regulators. The method presented here is easy to calculate and yields high phase margins. For most conditions, the regulator has a phase margin between 60 and 90 degrees. The method presented here ignores the effects of the slope compensation that is internal to the TPS54623. Since the slope compensation is ignored, the actual crossover frequency is usually lower than the cross over frequency used in the calculations.
First, the modulator pole, fpmod, and the esr zero, fzmod must be calculated using Equation 31 and Equation 32. For Cout, use a derated value of 75 µF. use Equation 33 and Equation 34 to estimate a starting point for the closed loop crossover frequency fco. Then the required compensation components may be derived. For this design example, fpmod is 3.86 kHz and fzmod is 707.4 kHz. Equation 33 is the geometric mean of the modulator pole and the esr zero and Equation 34 is the geometric mean of the modulator pole and one half the switching frequency. Use a frequency near the lower of these two values as the intended crossover frequency fco. In this case Equation 33 yields 52.2 kHz and Equation 34 yields 30.4 kHz. The lower value is 30.4 kHz. A slightly higher frequency of 30 kHz is chosen as the intended crossover frequency.
Now the compensation components can be calculated. First calculate the value for R2 which sets the gain of the compensated network at the crossover frequency. Use Equation 35 to determine the value of R2.
Next calculate the value of C3. Together with R2, C3 places a compensation zero at the modulator pole frequency. Equation 36 to determine the value of C3.
Using Equation 35 and Equation 36 the standard values for R4 and C4 are 3.74 kΩ and 0.01 µF.
An additional high frequency pole can be used if necessary by adding a capacitor in parallel with the series combination of R4 and C4. The pole frequency can be placed at the ESR zero frequency of the output capacitor as given by Equation 12. Use Equation 37 to calculate the required capacitor value for C5.
The device is designed to operate from an input-voltage supply range between 4.5 V and 17 V when the VIN and PVIN pins are connected to the same voltage source. This input supply should be well regulated. If the input supply is located more than a few inches from the converter, additional bulk capacitance may be required in addition to the ceramic bypass capacitors. An electrolytic capacitor with a value of 100 μF is a typical choice.
TPS54623 can be operated with independent voltage sources for the VIN and PVIN inputs. The voltage range for the VIN pin is 4.5 to 17 V. The voltage range for PVIN is 1.7 V to 17 V. Both of these input supplies should be well regulated. If the input supply is located more than a few inches from the converter, additional bulk capacitance may be required in addition to the ceramic bypass capacitors for PVIN.