SLVSB71E February   2012  – September 2016 TLV62150 , TLV62150A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application Schematic
      2.      Efficiency vs Output Current
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Enable / Shutdown (EN)
      2. 8.3.2 Soft Start / Tracking (SS/TR)
      3. 8.3.3 Power Good (PG)
      4. 8.3.4 Pin-Selectable Output Voltage (DEF)
      5. 8.3.5 Frequency Selection (FSW)
      6. 8.3.6 Undervoltage Lockout (UVLO)
      7. 8.3.7 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pulse Width Modulation (PWM) Operation
      2. 8.4.2 Power Save Mode Operation
      3. 8.4.3 100% Duty-Cycle Operation
      4. 8.4.4 Current Limit and Short Circuit Protection
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Programming the Output Voltage
        2. 9.2.2.2 External Component Selection
          1. 9.2.2.2.1 Inductor Selection
          2. 9.2.2.2.2 Capacitor Selection
            1. 9.2.2.2.2.1 Output Capacitor
            2. 9.2.2.2.2.2 Input Capacitor
            3. 9.2.2.2.2.3 Soft-Start Capacitor
        3. 9.2.2.3 Tracking Function
        4. 9.2.2.4 Output Filter and Loop Stability
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 LED Power Supply
      2. 9.3.2 Active Output Discharge
      3. 9.3.3 Inverting Power Supply
      4. 9.3.4 Various Output Voltages
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Related Links
    3. 12.3 Documentation Support
      1. 12.3.1 Related Documentation
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Community Resources
    6. 12.6 Trademarks
    7. 12.7 Electrostatic Discharge Caution
    8. 12.8 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

8.4.3 100% Duty-Cycle Operation

The duty cycle of the buck converter is given by D=Vout/Vin and increases as the input voltage comes close to the output voltage. In this case, the device starts 100% duty cycle operation turning on the high-side switch 100% of the time. The high-side switch stays turned on as long as the output voltage is below the internal setpoint. This allows the conversion of small input to output voltage differences, for example, for longest operation time of battery-powered applications. In 100% duty cycle mode, the low-side FET is switched off.

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The minimum input voltage to maintain output voltage regulation, depending on the load current and the output voltage level, can be calculated as:

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Equation 3. TLV62150 TLV62150A SLVSAG7_eqvinmin.gif

where

  • IOUT is the output current.
  • RDS(on) is the RDS(on) of the high-side FET.
  • RL is the DC resistance of the inductor used.

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