SLVSBD4E May   2012  – September 2021 TPS55340

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Operation
      2. 7.3.2 Switching Frequency
      3. 7.3.3 Overcurrent Protection and Frequency Foldback
        1. 7.3.3.1 Minimum On-Time and Pulse Skipping
      4. 7.3.4 Voltage Reference and Setting Output Voltage
      5. 7.3.5 Soft-Start
      6. 7.3.6 Slope Compensation
      7. 7.3.7 Enable and Thermal Shutdown
      8. 7.3.8 Undervoltage Lockout (UVLO)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation With VIN < 2.9 V (Minimum VIN)
      2. 7.4.2 Operation With EN Control
      3. 7.4.3 Operation at Light Loads
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Boost Converter
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Custom Design with WEBENCH Tools
          2. 8.2.1.2.2  Selecting the Switching Frequency (R4)
          3. 8.2.1.2.3  Determining the Duty Cycle
          4. 8.2.1.2.4  Selecting the Inductor (L1)
          5. 8.2.1.2.5  Computing the Maximum Output Current
          6. 8.2.1.2.6  Selecting the Output Capacitors (C8, C9, C10)
          7. 8.2.1.2.7  Selecting the Input Capacitors (C2, C7)
          8. 8.2.1.2.8  Setting Output Voltage (R1, R2)
          9. 8.2.1.2.9  Setting the Soft-start Time (C7)
          10. 8.2.1.2.10 Selecting the Schottky Diode (D1)
          11. 8.2.1.2.11 Compensating the Control Loop (R3, C4, C5)
        3. 8.2.1.3 Application Curves
      2. 8.2.2 SEPIC Converter
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1  Selecting the Switching Frequency (R4)
          2. 8.2.2.2.2  Duty Cycle
          3. 8.2.2.2.3  Selecting the Inductor (L1)
          4. 8.2.2.2.4  Calculating the Maximum Output Current
          5. 8.2.2.2.5  Selecting the Output Capacitors (C8, C9, C10)
          6. 8.2.2.2.6  Selecting the Series Capacitor (C6)
          7. 8.2.2.2.7  Selecting the Input Capacitor (C2, C7)
          8. 8.2.2.2.8  Selecting the Schottky Diode (D1)
          9. 8.2.2.2.9  Setting the Output Voltage (R1, R2)
          10. 8.2.2.2.10 Setting the Soft-start Time (C3)
          11. 8.2.2.2.11 MOSFET Rating Considerations
          12. 8.2.2.2.12 Compensating the Control Loop (R3, C4)
        3. 8.2.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
        1. 11.1.2.1 Custom Design with WEBENCH Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
Compensating the Control Loop (R3, C4, C5)

The TPS55340 requires external compensation which allows the loop response to be optimized for each application. The COMP pin is the output of the internal error amplifier. An external resistor R3 and ceramic capacitor C4 are connected to the COMP pin to provide a pole and a zero, shown in Figure 8-1. This pole and zero, along with the inherent pole and zero of a boost converter, determine the closed-loop frequency response. This is important for converter stability and transient response. Loop compensation should be designed for the minimum operating voltage.

The following equations summarize the loop equations for the TPS55340 configured as a CCM boost converter. They include the power stage output pole (ƒOUT) and the right-half-plane zero (ƒRHPZ) of a boost converter calculated with Equation 27 and Equation 28, respectively. When calculating ƒOUT, it is important to include the derating of ceramic output capacitors. In the example with an estimated 10.2-µF capacitance, these frequencies are calculated to be 980 kHz and 22.1 kHz, respectively. The dc gain (A) of the power stage is calculated with Equation 29 and is 39.9 dB in this design. The compensation pole (ƒP) and zero (ƒZ) generated by R3, C4, and internal transconductance amplifier are calculated with Equation 30 and Equation 31, respectively.

Most CCM boost converters will have a stable control loop if fZ is set slightly above ƒP through proper sizing of R3 and C4. A good starting point is C4 = 0.1 µF and R3 = 2 kΩ. Increasing R3 or reducing C4 increases the closed-loop bandwidth, and therefore improves the transient response. Adjusting R3 and C4 in the opposite direction increases the phase and gain margin of the loop, which improves loop stability. It is generally recommended to limit the bandwidth of the loop to the lower of either 1/5 of the switching frequency ƒSW or 1/3 the RHPZ frequency, ƒRHPZ shown in Equation 28. The spreadsheet tool located in the TPS55340 product folder at www.ti.com can also be used to aid in compensation design.

Equation 27. GUID-7D61E196-80A7-40D4-B39E-16006666DBC7-low.gif
Equation 28. GUID-6157199B-518A-4F85-9B5C-436E1251BDF3-low.gif
Equation 29. GUID-24F4C8ED-8E6E-4BC4-9B22-5688CDE05965-low.gif
Equation 30. GUID-685CF211-A0C5-4AE8-84CC-CE1EEFB8D01F-low.gif
Equation 31. GUID-E487FD2D-6BF1-4BB9-9040-3B0A76ECB5A4-low.gif
Equation 32. GUID-4E99C68A-78B0-4182-91BD-E43EE3631C53-low.gif
Equation 33. GUID-241603A6-AAC7-4D61-8DF1-7AEE8A99A85E-low.gif

where

  • COUT is the equivalent output capacitor (COUT= C8 + C9 + C10)
  • ROUT is the equivalent load resistance (VOUT/IOUT)
  • Gea is the error amplifier transconductance located in Section 6.5
  • RSENSE (15 mΩ, typical) is the sense resistor in the current control loop
  • ƒco1 and ƒco2 are possible bandwidths.

An additional capacitor from the COMP pin to GND (C5) can be used to place a high-frequency pole in the control loop. This is not always necessary with ceramic output capacitors. If a nonceramic output capacitor is used, there is an additional zero (fZESR) in the control loop which can be calculated with Equation 35. The value of C5 and the pole created by C5 can be calculated with Equation 36 and Equation 34, respectively. Finally, if more phase margin is needed, an additional zero (fZFF) can be added by placing a capacitor (CFF) in parallel with the top feedback resistor R1. It is recommended to place the zero at the target cross-over frequency or higher. The feed-forward capacitor also adds a pole at a higher frequency. The recommended value of CFF can be calculated with Equation 37.

Equation 34. GUID-A08E012C-AF9F-4A3C-B2B5-204776EA7714-low.gif
Equation 35. GUID-6E49692C-4E28-4134-AE44-40392C8D7404-low.gif
Equation 36. GUID-B1C0CDBA-3E21-4190-B46B-D51AC17368FD-low.gif
Equation 37. GUID-03D90975-46F3-4D8C-8CE2-ACDCF5FEBF9B-low.gif

where

  • RESR is the ESR of the output capacitor

If a network measurement tool is available, the most accurate compensation design can be achieved following this procedure. The power stage frequency response is first measured using a network analyzer at the minimum 5-V input and maximum 800-mA load. This measurement is shown in Figure 8-2. In this design only one pole and one zero are used, so the maximum phase increase from the compensation will be 180 degrees. For a
60-degree phase margin, the power stage phase must be –120 degrees at its lowest point. Based on the target 6-kHz bandwidth, the measured power stage gain, KPS(fBW), is 24.84 dB and the phase is –110.3 degrees.

GUID-268BA8FF-5562-4AD2-A43D-E5CB18D88BB2-low.pngFigure 8-2 Power Stage Gain and Phase of the Boost Converter

R3 is then chosen to set the compensation gain to be the reciprocal of the power stage gain at the target bandwidth using Equation 38. C4 is then chosen to place a zero at 1/10 the target bandwidth with Equation 39. In this case, R3 is calculated to be 2.56 kΩ and the nearest standard value of 2.55 kΩ is used. C4 is calculated at 0.104 µF and the nearest standard value of 0.100 µF is used. Although not necessary because this design uses all ceramic capacitors, a 100-pF capacitor is selected for C5 to add a high-frequency pole at a frequency 100 times the target bandwidth.

Equation 38. GUID-F76CCC78-9EF9-4193-AC33-51B047CA8305-low.gif
Equation 39. GUID-59CE836C-39FC-4D52-B5CB-30D21A6B5487-low.gif