SLVSCB2D October   2013  – April 2018 TPS7B67-Q1

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Adjustable Output Option
      2.      Fixed Output Option
  4. Revision History
  5. Device Comparison
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Enable (EN)
      2. 8.3.2 Regulated Output (VOUT)
      3. 8.3.3 Power-On-Reset (RESET)
      4. 8.3.4 Reset Delay Timer (DELAY)
      5. 8.3.5 Adjustable Output Voltage (ADJ for TPS7B6701)
      6. 8.3.6 Undervoltage Shutdown
      7. 8.3.7 Thermal Shutdown
      8. 8.3.8 Thermal Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation With VIN < 4 V
      2. 8.4.2 Operation With EN Control
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Power Dissipation and Thermal Considerations
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Dropout Recovery
      1. 10.1.1 LDO Dropout Recovery Explained
      2. 10.1.2 TPS7B67xx-Q1 Dropout During Startup
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Enhanced Thermal Pad
      2. 11.1.2 Package Mounting
      3. 11.1.3 Board Layout Recommendations to Improve PSRR and Noise Performance
      4. 11.1.4 Additional Layout Considerations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Typical Characteristics

TPS7B6701-Q1 TPS7B6733-Q1 TPS7B6750-Q1 C001_SLVSCB2.png
Figure 1. Line Regulation
(VO = 1.5 V, IL = 100 mA)
TPS7B6701-Q1 TPS7B6733-Q1 TPS7B6750-Q1 C003_SLVSCB2.png
Figure 3. Quiescent Current vs Input Voltage
(VO = 1.5 V)
TPS7B6701-Q1 TPS7B6733-Q1 TPS7B6750-Q1 C005_SLVSCB2.png
Figure 5. Quiescent Current vs Input Voltage
(VO = 18 V)
TPS7B6701-Q1 TPS7B6733-Q1 TPS7B6750-Q1 C007_SLVSCB2.png
Figure 7. Load Regulation
(VI = 14 V, VO = 1.5 V)
TPS7B6701-Q1 TPS7B6733-Q1 TPS7B6750-Q1 C009_SLVSCB2.png
Figure 9. ESR Stability vs Load Capacitance
(VO ≥ 2.5 V)
TPS7B6701-Q1 TPS7B6733-Q1 TPS7B6750-Q1 C011_SLVSCB2.png
Figure 11. Output Voltage vs Supply Voltage
(Fixed 3.3-V Version, IL = 0)
TPS7B6701-Q1 TPS7B6733-Q1 TPS7B6750-Q1 C013_SLVSCB2.png
Figure 13. Short to GND Current-Limit vs Temperature
TPS7B6701-Q1 TPS7B6733-Q1 TPS7B6750-Q1 scope_load_transient_slvscb2.gif
Figure 15. Load Transient
10-µF Ceramic Output Capacitor
TPS7B6701-Q1 TPS7B6733-Q1 TPS7B6750-Q1 C002_SLVSCB2.png
Figure 2. Ground Current vs Output Current
(VI = 14 V, VO = 1.5 V)
TPS7B6701-Q1 TPS7B6733-Q1 TPS7B6750-Q1 C004_SLVSCB2.png
Figure 4. Ground Current vs Output Current
(VI = 24 V, VO = 18 V)
TPS7B6701-Q1 TPS7B6733-Q1 TPS7B6750-Q1 C006_SLVSCB2.png
Figure 6. Dropout Voltage vs Output Current
TPS7B6701-Q1 TPS7B6733-Q1 TPS7B6750-Q1 C008_SLVSCB2.png
Figure 8. ESR Stability vs Load Capacitance
(VO ≤ 2.5 V)
TPS7B6701-Q1 TPS7B6733-Q1 TPS7B6750-Q1 C010_SLVSCB2.png
Figure 10. Output Voltage vs Supply Voltage
(Fixed 5-V Version, IL = 0)
TPS7B6701-Q1 TPS7B6733-Q1 TPS7B6750-Q1 C012_SLVSCB2.png
Figure 12. Power-Supply Rejection Ratio vs Frequency
(VI = 14 V, CO = 47 µF, IL = 25 mA)
TPS7B6701-Q1 TPS7B6733-Q1 TPS7B6750-Q1 C014_SLVSCB2.png
Figure 14. Current-Limit vs Temperature