SLVSCN0C june   2014  – may 2023 TPS65263

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Revision History
  6. Device Comparison Table
  7. Pin Configuration and Functions
  8. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Adjusting the Output Voltage
      2. 8.3.2  Enable and Adjusting UVLO
      3. 8.3.3  Soft-Start Time
      4. 8.3.4  Power-Up Sequencing
      5. 8.3.5  V7V Low Dropout Regulator and Bootstrap
      6. 8.3.6  Out-of-Phase Operation
      7. 8.3.7  Output Overvoltage Protection (OVP)
      8. 8.3.8  Pulse Skipping Mode (PSM)
      9. 8.3.9  Slope Compensation
      10. 8.3.10 Overcurrent Protection
        1. 8.3.10.1 High-Side MOSFET Overcurrent Protection
        2. 8.3.10.2 Low-Side MOSFET Overcurrent Protection
      11. 8.3.11 Power Good
      12. 8.3.12 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Serial Interface Description
      2. 8.4.2 I2C Update Sequence
    5. 8.5 Register Maps
      1. 8.5.1 Register Description
      2. 8.5.2 VOUT1_SEL: Vout1 Voltage Selection Register (offset = 0x00H)
      3. 8.5.3 VOUT2_SEL: Vout2 Voltage Selection Register (offset = 0x01H)
      4. 8.5.4 VOUT3_SEL: Vout3 Voltage Selection Register (offset = 0x02H)
      5. 8.5.5 VOUT1_COM: Buck1 Command Register (offset = 0x03H)
      6. 8.5.6 VOUT2_COM: Buck2 Command Register (offset = 0x04H)
      7. 8.5.7 VOUT3_COM: Buck3 Command Register (offset = 0x05H)
      8. 8.5.8 SYS_STATUS: System Status Register (offset = 0x06H)
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Output Inductor Selection
        2. 9.2.2.2 Output Capacitor Selection
        3. 9.2.2.3 Input Capacitor Selection
        4. 9.2.2.4 Loop Compensation
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
INPUT SUPPLY VOLTAGE
VINInput voltage range4.518V
UVLOVIN undervoltage lockoutVIN rising44.254.5V
VIN falling3.53.754V
Hysteresis500mV
IDDSDNShutdown supply currentEN1 = EN2 = EN3 = 0 V8µA
IDDQ_NSWInput quiescent current without buck1/2/3 switchingEN1 = EN2 = EN3 = 5 V,
FB1 = FB2 = FB3 = 0.8 V
740µA
IDDQ_NSW1EN1 = 5 V, EN2 = EN3 = 0 V,
FB1 = 0.8 V
360µA
IDDQ_NSW2EN2 = 5 V, EN1 = EN3 = 0 V,
FB2 = 0.8 V
380µA
IDDQ_NSW3EN3 = 5 V, EN1 = EN2 = 0 V,
FB3 = 0.8 V
380µA
V7VV7V LDO output voltageV7V load current = 0 A66.36.6V
IOCP_V7VV7V LDO current limit185mA
FEEDBACK VOLTAGE REFERENCE
VFBFeedback voltageVCOMP = 1.2 V, TJ = 25°C0.5950.60.605V
VCOMP = 1.2 V, TJ = –40°C to 125°C0.5940.60.606V
VLINEREG_BUCKLine regulation-DC(1)IOUT1 = 1.5 A, IOUT2 = 1 A, IOUT3 = 1 A,
5 V < PVINx < 18 V
0.002%/V
VLOADREG_BUCKLoad regulation-DC(1)IOUTx = (10-100%) × IOUTx_max0.02%/A
BUCK1, BUCK2, BUCK3
VENXHEN1/2/3 high level input voltage1.21.26V
VENXLEN1/2/3 low level input voltage1.11.15V
IENX1EN1/2/3 pullup currentENx = 1 V3.8µA
IENX2EN1/2/3 pullup currentENx = 1.5 V6.8µA
IENhysHysteresis current3µA
ISSXSoft start charging current4.356µA
TON_MINMinimum on time80100ns
Gm_EAError amplifier trans-conductance–2 µA < ICOMPX < 2 µA300µS
Gm_PS1/2/3COMP1/2/3 voltage to inductor current Gm(1)ILX = 0.5 A7.4A/V
ILIMIT1Buck1 peak inductor current limit4.55.56.5A
ILIMITSOURCE1Buck1 low side source current limit4.4A
ILIMITSINK1Buck1 low side sink current limit1.3
ILIMIT2/3buck2/3 peak inductor current limit2.63.34A
ILIMITSOURCE2/3Buck2/3 low side source current limit2.5
ILIMITSINK2/3Buck2/3 low side sink current limit1A
Rdson_HS1Buck1 high-side switch resistanceVIN = 12 V105mΩ
Rdson_LS1Buck1 low-side switch resistanceVIN = 12 V65mΩ
Rdson_HS2Buck2 high-side switch resistanceVIN = 12 V140mΩ
Rdson_LS2Buck2 low-side switch resistanceVIN = 12 V90mΩ
Rdson_HS3Buck3 high-side switch resistanceVIN = 12 V140mΩ
Rdson_LS3Buck3 low-side switch resistanceVIN = 12 V90mΩ
HICCUP TIMING
THiccup_waitOver current wait time(1)0.5ms
THiccup_reHiccup time before restart(1)14ms
OSCILLATOR
FSWSwitching frequency550600650kHz
THERMAL PROTECTION
TTRIP_OTPThermal protection trip point(1)Temperature rising160°C
THYST_OTPThermal protection Hysteresis(1)Hysteresis20°C
I2C INTERFACE
AddrAddress(2)0x60H
VIH SDA,SCLInput high voltage2V
VIL SDA,SCLInput low voltage0.4V
IIInput currentSDA, SCL, VI = 0.4 to 4.5 V–1010µA
VOL SDASDA output low voltageSDA open drain, IOL = 4 mA0.4V
ƒ(SCL)Maximum SCL clock frequency(2)400kHz
tBUFBus free time between a STOP and START condition(2)1.3µs
tHD_STAHold time (repeated) START condition(2)0.6µs
tSU_STOSetup time for STOP condition(2)0.6µs
tLOWLOW Period of the SCL Clock(2)1.3µs
tHIGHHIGH period of the SCL clock(2)0.6µs
tSU_STASetup time for a repeated START condition(2)0.6µs
tSU_DATData setup time(2)0.1µs
tHD_DATData hold time(2)00.9µs
tRCLRise time of SCL signal(2)Capacitance of one bus line (pF)20 + 0.1CB300ns
tRCL1Rise time of SCL signal after a repeated START condition and after an acknowledge BIT(2)Capacitance of one bus line (pF)20 + 0.1CB300ns
tFCLFall time of SCL signal(2)Capacitance of one bus line (pF)20 + 0.1CB300ns
tRDARise time of SDA signal(2)Capacitance of one bus line (pF)20 + 0.1CB300ns
tFDAFall time of SDA signal(2)Capacitance of one bus line (pF)20 + 0.1CB300ns
CBCapacitance of bus line(SCL and SDA)(2)400pF
Lab validation result.
Not production tested.