SLVSCN0C june   2014  – may 2023 TPS65263

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Adjusting the Output Voltage
      2. 8.3.2  Enable and Adjusting UVLO
      3. 8.3.3  Soft-Start Time
      4. 8.3.4  Power-Up Sequencing
      5. 8.3.5  V7V Low Dropout Regulator and Bootstrap
      6. 8.3.6  Out-of-Phase Operation
      7. 8.3.7  Output Overvoltage Protection (OVP)
      8. 8.3.8  Pulse Skipping Mode (PSM)
      9. 8.3.9  Slope Compensation
      10. 8.3.10 Overcurrent Protection
        1. 8.3.10.1 High-Side MOSFET Overcurrent Protection
        2. 8.3.10.2 Low-Side MOSFET Overcurrent Protection
      11. 8.3.11 Power Good
      12. 8.3.12 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Serial Interface Description
      2. 8.4.2 I2C Update Sequence
    5. 8.5 Register Maps
      1. 8.5.1 Register Description
      2. 8.5.2 VOUT1_SEL: Vout1 Voltage Selection Register (offset = 0x00H)
      3. 8.5.3 VOUT2_SEL: Vout2 Voltage Selection Register (offset = 0x01H)
      4. 8.5.4 VOUT3_SEL: Vout3 Voltage Selection Register (offset = 0x02H)
      5. 8.5.5 VOUT1_COM: Buck1 Command Register (offset = 0x03H)
      6. 8.5.6 VOUT2_COM: Buck2 Command Register (offset = 0x04H)
      7. 8.5.7 VOUT3_COM: Buck3 Command Register (offset = 0x05H)
      8. 8.5.8 SYS_STATUS: System Status Register (offset = 0x06H)
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Output Inductor Selection
        2. 9.2.2.2 Output Capacitor Selection
        3. 9.2.2.3 Input Capacitor Selection
        4. 9.2.2.4 Loop Compensation
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

7.2 ESD Ratings

MINMAXUNIT
V(ESD)Electrostatic dischargeHuman body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)–20002000V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2)–500500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.