SLVSD05G March   2016  – August 2024 TPS56C215

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  PWM Operation and D-CAP3™ Control Mode
      2. 6.3.2  Eco-mode Control
      3. 6.3.3  4.7-V LDO
      4. 6.3.4  MODE Selection
      5. 6.3.5  Soft Start and Prebiased Soft Start
      6. 6.3.6  Enable and Adjustable UVLO
      7. 6.3.7  Power Good
      8. 6.3.8  Overcurrent Protection and Undervoltage Protection
      9. 6.3.9  UVLO Protection
      10. 6.3.10 Thermal Shutdown
      11. 6.3.11 Output Voltage Discharge
    4. 6.4 Device Functional Modes
      1. 6.4.1 Light Load Operation
      2. 6.4.2 Standby Operation
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 External Component Selection
          1. 7.2.2.1.1 Output Voltage Set Point
          2. 7.2.2.1.2 Switching Frequency and MODE Selection
          3. 7.2.2.1.3 Inductor Selection
          4. 7.2.2.1.4 Output Capacitor Selection
          5. 7.2.2.1.5 Input Capacitor Selection
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
      2. 8.1.2 Development Support
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Package Marking

6.3.7 Power Good

The Power Good (PGOOD) pin is an open-drain output. After the FB pin voltage is between 93% and 107% of the internal reference voltage (VREF), the PGOOD is de-asserted and floats after a 200-µs de-glitch time. A pullup resistor of 10 kΩ is recommended to pull it up to VREG5. The PGOOD pin is pulled low when the FB pin voltage is lower than VUVP or greater than VOVP threshold, in an event of thermal shutdown, or during the soft-start period.