SLVSD76C February   2016  – July 2017 TPS22918

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical DC Characteristics
    8. 6.8 Typical AC Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 On and Off Control
      2. 8.3.2 Quick Output Discharge (QOD)
        1. 8.3.2.1 QOD when System Power is Removed
        2. 8.3.2.2 Internal QOD Considerations
      3. 8.3.3 Adjustable Rise Time (CT)
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input Capacitor (CIN)
        2. 9.2.2.2 Output Capacitor (CL) (Optional)
        3. 9.2.2.3 Shutdown Sequencing During Unexpected System Power Loss
        4. 9.2.2.4 VIN to VOUT Voltage Drop
        5. 9.2.2.5 Inrush Current
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Developmental Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

11 Layout

11.1 Layout Guidelines

VIN and VOUT traces should be as short and wide as possible to accommodate for high current.

The VIN pin should be bypassed to ground with low ESR ceramic bypass capacitors. The typical recommended bypass capacitance is 1-µF ceramic with X5R or X7R dielectric. This capacitor must be placed as close to the device pins as possible.

11.2 Layout Example

TPS22918 Layout_SLVSD76.gif Figure 32. Recommended Board Layout

11.3 Thermal Considerations

For best performance, all traces must be as short as possible. To be most effective, the input and output capacitors must be placed close to the device to minimize the effects that parasitic trace inductances may have on normal and short-circuit operation. Using wide traces for VIN, VOUT, and GND helps minimize the parasitic electrical effects along with minimizing the case to ambient thermal impedance.

The maximum IC junction temperature should be restricted to 125°C under normal operating conditions. To calculate the maximum allowable dissipation, PD(max) for a given output current and ambient temperature, use Equation 14:

Equation 14. TPS22918 Q5_PDmax2_slvsco0.gif

where

  • PD(MAX) = maximum allowable power dissipation
  • TJ(MAX) = maximum allowable junction temperature (125°C for the TPS22918)
  • TA = ambient temperature of the device
  • θJA = junction to air thermal impedance. Refer to the Thermal Information table. This parameter is highly dependent upon board layout.