The ADC12DJ3200 device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from DC to above 10 GHz. In dual-channel mode, the ADC12DJ3200 can sample up to 3200 MSPS and up to 6400 MSPS in single-channel mode. Programmable tradeoffs in channel count (dual-channel mode) and Nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets the needs of both high channel count or wide instantaneous signal bandwidth applications. Full-power input bandwidth (–3 dB) of 8.0 GHz, with usable frequencies exceeding the –3-dB point in both dual- and single-channel modes, allows direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.
The ADC12DJ3200 uses a high-speed JESD204B output interface with up to 16 serialized lanes and subclass-1 compliance for deterministic latency and multi-device synchronization. The serial output lanes support up to 12.8 Gbps and can be configured to trade-off bit rate and number of lanes. Innovative synchronization features, including noiseless aperture delay (TAD) adjustment and SYSREF windowing, simplify system design for phased array radar and MIMO communications. Optional digital down converters (DDCs) in dual-channel mode allow for reduction in interface rate (real and complex decimation modes) and digital mixing of the signal (complex decimation modes only).
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
ADC12DJ3200 | FCBGA (144) | 10.00 mm × 10.00 mm |
Changes from * Revision (June 2017) to A Revision
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
AGND | A1, A2, A3, A6, A7, B2, B3, B4, B5, B6, B7, C6, D1, D6, E1, E6, F2, F3, F6, G2, G3, G6, H1, H6, J1, J6, L2, L3, L4, L5, L6, L7, M1, M2, M3, M6, M7 | — | Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
BG | C3 | O | Band-gap voltage output. This pin is capable of sourcing only small currents and driving limited capacitive loads, as specified in the Recommended Operating Conditions table. This pin can be left disconnected if not used. |
CALSTAT | F7 | O | Foreground calibration status output or device alarm output. Functionality is programmed through CAL_STATUS_SEL. This pin can be left disconnected if not used. |
CALTRIG | E7 | I | Foreground calibration trigger input. This pin is only used if hardware calibration triggering is selected in CAL_TRIG_EN, otherwise software triggering is performed using CAL_SOFT_TRIG. Tie this pin to GND if not used. |
CLK+ | F1 | I | Device (sampling) clock positive input. The clock signal is strongly recommended to be AC-coupled to this input for best performance. In single-channel mode, the analog input signal is sampled on both the rising and falling edges. In dual-channel mode, the analog signal is sampled on the rising edge. This differential input has an internal untrimmed 100-Ω differential termination and is self-biased to the optimal input common-mode voltage as long as DEVCLK_LVPECL_EN is set to 0. |
CLK– | G1 | I | Device (sampling) clock negative input. TI strongly recommends using AC-coupling for best performance. |
DA0+ | E12 | O | High-speed serialized data output for channel A, lane 0, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used. |
DA0– | F12 | O | High-speed serialized data output for channel A, lane 0, negative connection. This pin can be left disconnected if not used. |
DA1+ | C12 | O | High-speed serialized data output for channel A, lane 1, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used. |
DA1– | D12 | O | High-speed serialized data output for channel A, lane 1, negative connection. This pin can be left disconnected if not used. |
DA2+ | A10 | O | High-speed serialized-data output for channel A, lane 2, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used. |
DA2– | A11 | O | High-speed serialized-data output for channel A, lane 2, negative connection. This pin can be left disconnected if not used. |
DA3+ | A8 | O | High-speed serialized-data output for channel A, lane 3, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used. |
DA3– | A9 | O | High-speed serialized-data output for channel A, lane 3, negative connection. This pin can be left disconnected if not used. |
DA4+ | E11 | O | High-speed serialized data output for channel A, lane 4, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used. |
DA4– | F11 | O | High-speed serialized data output for channel A, lane 4, negative connection. This pin can be left disconnected if not used. |
DA5+ | C11 | O | High-speed serialized data output for channel A, lane 5, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used. |
DA5– | D11 | O | High-speed serialized data output for channel A, lane 5, negative connection. This pin can be left disconnected if not used. |
DA6+ | B10 | O | High-speed serialized data output for channel A, lane 6, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used. |
DA6– | B11 | O | High-speed serialized data output for channel A, lane 6, negative connection. This pin can be left disconnected if not used. |
DA7+ | B8 | O | High-speed serialized data output for channel A, lane 7, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used. |
DA7– | B9 | O | High-speed serialized data output for channel A, lane 7, negative connection. This pin can be left disconnected if not used. |
DB0+ | H12 | O | High-speed serialized data output for channel B, lane 0, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used. |
DB0– | G12 | O | High-speed serialized data output for channel B, lane 0, negative connection. This pin can be left disconnected if not used. |
DB1+ | K12 | O | High-speed serialized data output for channel B, lane 1, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used. |
DB1– | J12 | O | High-speed serialized data output for channel B, lane 1, negative connection. This pin can be left disconnected if not used. |
DB2+ | M10 | O | High-speed serialized data output for channel B, lane 2, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used. |
DB2– | M11 | O | High-speed serialized data output for channel B, lane 2, negative connection. This pin can be left disconnected if not used. |
DB3+ | M8 | O | High-speed serialized data output for channel B, lane 3, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used. |
DB3– | M9 | O | High-speed serialized data output for channel B, lane 3, negative connection. This pin can be left disconnected if not used. |
DB4+ | H11 | O | High-speed serialized data output for channel B, lane 4, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used. |
DB4– | G11 | O | High-speed serialized data output for channel B, lane 4, negative connection. This pin can be left disconnected if not used. |
DB5+ | K11 | O | High-speed serialized data output for channel B, lane 5, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used. |
DB5– | J11 | O | High-speed serialized data output for channel B, lane 5, negative connection. This pin can be left disconnected if not used. |
DB6+ | L10 | O | High-speed serialized data output for channel B, lane 6, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used. |
DB6– | L11 | O | High-speed serialized data output for channel B, lane 6, negative connection. This pin can be left disconnected if not used. |
DB7+ | L8 | O | High-speed serialized data output for channel B, lane 7, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used. |
DB7– | L9 | O | High-speed serialized data output for channel B, lane 7, negative connection. This pin can be left disconnected if not used. |
DGND | A12, B12, D9, D10, F9, F10, G9, G10, J9, J10, L12, M12 | — | Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board. |
INA+ | A4 | I | Channel A analog input positive connection. INA± is recommended for use in single channel mode for optimal performance. The differential full-scale input voltage is determined by the FS_RANGE_A register (see the Full-Scale Voltage (VFS) Adjustment section). This input is terminated to ground through a 50-Ω termination resistor. The input common-mode voltage is typically be set to 0 V (GND) and must follow the recommendations in the Recommended Operating Conditions table. This pin can be left disconnected if not used. |
INA– | A5 | I | Channel A analog input negative connection. INA± is recommended for use in single channel mode for optimal performance. See INA+ (pin A4) for detailed description. This input is terminated to ground through a 50-Ω termination resistor. This pin can be left disconnected if not used. |
INB+ | M4 | I | Channel B analog input positive connection. INA± is recommended for use in single channel mode for optimal performance. The differential full-scale input voltage is determined by the FS_RANGE_B register (see the Full-Scale Voltage (VFS) Adjustment section). This input is terminated to ground through a 50-Ω termination resistor. The input common-mode voltage is typically be set to 0 V (GND) and must follow the recommendations in the Recommended Operating Conditions table. This pin can be left disconnected if not used. |
INB– | M5 | I | Channel B analog input negative connection. INA± is recommended for use in single channel mode for optimal performance. See INA+ (pin A4) for detailed description. This input is terminated to ground through a 50-Ω termination resistor. This pin can be left disconnected if not used. |
NCOA0 | C7 | I | LSB of NCO selection control for DDC A. NCOA0 and NCOA1 select which NCO, of a possible four NCOs, is used for digital mixing when using a complex output JMODE. The remaining unselected NCOs continue to run to maintain phase coherency and can be swapped in by changing the values of NCOA0 and NCOA1 (when CMODE = 1). This pin is an asynchronous input. See the NCO Fast Frequency Hopping (FFH) and NCO Selection sections for more information. Tie this pin to GND if not used. |
NCOA1 | D7 | I | MSB of NCO selection control for DDC A. Tie this pin to GND if not used. |
NCOB0 | K7 | I | LSB of NCO selection control for DDC B. NCOB0 and NCOB1 select which NCO, of a possible four NCOs, is used for digital mixing when using a complex output JMODE. The remaining unselected NCOs continue to run to maintain phase coherency and can be swapped in by changing the values of NCOB0 and NCOB1 (when CMODE = 1). This pin is an asynchronous input. See the NCO Fast Frequency Hopping (FFH) and NCO Selection sections for more information. Tie this pin to GND if not used. |
NCOB1 | J7 | I | MSB of NCO selection control for DDC B. Tie this pin to GND if not used. |
ORA0 | C8 | O | Fast overrange detection status for channel A for the OVR_T0 threshold. When the analog input exceeds the threshold programmed into OVR_T0, this status indicator goes high. The minimum pulse duration is set by OVR_N. See the ADC Overrange Detection section for more information. This pin can be left disconnected if not used. |
ORA1 | D8 | O | Fast overrange detection status for channel A for the OVR_T1 threshold. When the analog input exceeds the threshold programmed into OVR_T1, this status indicator goes high. The minimum pulse duration is set by OVR_N. See the ADC Overrange Detection section for more information. This pin can be left disconnected if not used. |
ORB0 | K8 | O | Fast overrange detection status for channel B for the OVR_T0 threshold. When the analog input exceeds the threshold programmed into OVR_T0, this status indicator goes high. The minimum pulse duration is set by OVR_N. See the ADC Overrange Detection section for more information. This pin can be left disconnected if not used. |
ORB1 | J8 | O | Fast overrange detection status for channel B for the OVR_T1 threshold. When the analog input exceeds the threshold programmed into OVR_T1, this status indicator goes high. The minimum pulse duration is set by OVR_N. See the ADC Overrange Detection section for more information. This pin can be left disconnected if not used. |
PD | K6 | I | This pin disables all analog circuits and serializer outputs when set high for temperature diode calibration only. Do not use this pin to power down the device for power savings. Tie this pin to GND during normal operation. For information regarding reliable serializer operation, see the Power-Down Modes section. |
SCLK | F8 | I | Serial interface clock. This pin functions as the serial-interface clock input that clocks the serial programming data in and out. The Using the Serial Interface section describes the serial interface in more detail. Supports 1.1-V to 1.9-V CMOS levels. |
SCS | E8 | I | Serial interface chip select active low input. The Using the Serial Interface section describes the serial interface in more detail. Supports 1.1-V to 1.9-V CMOS levels. This pin has a 82-kΩ pullup resistor to VD11. |
SDI | G8 | I | Serial interface data input. The Using the Serial Interface section describes the serial interface in more detail. Supports 1.1-V to 1.9-V CMOS levels. |
SDO | H8 | O | Serial interface data output. The Using the Serial Interface section describes the serial interface in more detail. This pin is high impedance during normal device operation. This pin outputs 1.9-V CMOS levels during serial interface read operations. This pin can be left disconnected if not used. |
SYNCSE | C2 | I | Single-ended JESD204B SYNC signal. This input is an active low input that is used to initialize the JESD204C serial link in 8B/10B modes when SYNC_SEL is set to 0. When toggled low this input initiates code group synchronization (see the Code Group Synchronization (CGS) section). After code group synchronization, this input must be toggled high to start the initial lane alignment sequence (see the Initial Lane Alignment Sequence (ILAS) section). A differential SYNC signal can be used instead by setting SYNC_SEL to 1 and using TMSTP± as a differential SYNC input. Tie this pin to GND if differential SYNC (TMSTP±) is used as the JESD204B SYNC signal. |
SYSREF+ | K1 | I | The SYSREF positive input is used to achieve synchronization and deterministic latency across the JESD204B interface. This differential input (SYSREF+ to SYSREF–) has an internal untrimmed 100-Ω differential termination and can be AC-coupled when SYSREF_LVPECL_EN is set to 0. This input is self-biased when SYSREF_LVPECL_EN is set to 0. The termination changes to 50 Ω to ground on each input pin (SYSREF+ and SYSREF–) and can be DC-coupled when SYSREF_LVPECL_EN is set to 1. This input is not self-biased when SYSREF_LVPECL_EN is set to 1 and must be biased externally to the input common-mode voltage range provided in the Recommended Operating Conditions table. |
SYSREF– | L1 | I | SYSREF negative input |
TDIODE+ | K2 | I | Temperature diode positive (anode) connection. An external temperature sensor can be connected to TDIODE+ and TDIODE– to monitor the junction temperature of the device. This pin can be left disconnected if not used. |
TDIODE– | K3 | I | Temperature diode negative (cathode) connection. This pin can be left disconnected if not used. |
TMSTP+ | B1 | I | Timestamp input positive connection or differential JESD204B SYNC positive connection. This input is a timestamp input, used to mark a specific sample, when TIMESTAMP_EN is set to 1. This differential input is used as the JESD204B SYNC signal input when SYNC_SEL is set 1. This input can be used as both a timestamp and differential SYNC input at the same time, allowing feedback of the SYNC signal using the timestamp mechanism. TMSTP± uses active low signaling when used as a JESD204B SYNC. For additional usage information, see theTimestamp section.
TMSTP_RECV_EN must be set to 1 to use this input. This differential input (TMSTP+ to TMSTP–) has an internal untrimmed 100-Ω differential termination and can be AC-coupled when TMSTP_LVPECL_EN is set to 0. The termination changes to 50 Ω to ground on each input pin (TMSTP+ and TMSTP–) and can be DC coupled when TMSTP_LVPECL_EN is set to 1. This pin is not self-biased and therefore must be externally biased for both AC- and DC-coupled configurations. The common-mode voltage must be within the range provided in the Recommended Operating Conditions table when both AC and DC coupled. This pin can be left disconnected and disabled (TMSTP_RECV_EN = 0) if SYNCSE is used for JESD204B SYNC and timestamp is not required. |
TMSTP– | C1 | I | Timestamp input positive connection or differential JESD204B SYNC negative connection. This pin can be left disconnected and disabled (TMSTP_RECV_EN = 0) if SYNCSE is used for JESD204B SYNC and timestamp is not required. |
VA11 | C5, D2, D3, D5, E5, F5, G5, H5, J2, J3, J5, K5 | I | 1.1-V analog supply |
VA19 | C4, D4, E2, E3, E4, F4, G4, H2, H3, H4, J4, K4 | I | 1.9-V analog supply |
VD11 | C9, C10, E9, E10, G7, H7, H9, H10, K9, K10 | I | 1.1-V digital supply |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Supply Voltage Range | VA19(2) | -0.3 | 2.35 | V |
VA11(2) | -0.3 | 1.32 | V | |
VD11(3) | -0.3 | 1.32 | V | |
Voltage between VD11 and VA11 | -1.32 | 1.32 | V | |
Voltage between AGND and DGND | -0.1 | 0.1 | V | |
Terminal Voltage Range | DA0...7+, DA0...7-, DB0...7+, DB0...7-, TMSTP+, TMSTP–(3) | -0.5 | min(1.32, VD11+0.5) | V |
CLK+, CLK–, SYSREF+, SYSREF–(2) | -0.5 | min(1.32, VA11+0.5) | V | |
BG, TDIODE+, TDIODE–(2) | -0.5 | min(2.35, VA19+0.5) | V | |
INA+, INA–, INB+, INB–(2) | -1 | 1 | V | |
CALSTAT, CALTRIG, NCOA0, NCOA1, NCOB0, NCOB1, ORA0, ORA1, ORB0, ORB1, PD, SCLK, SCS, SDI, SDO, SYNCSE(2) | -0.5 | VA19+0.5 | V | |
Peak input current (any input except INA+, INA–, INB+, INB–) | -25 | 25 | mA | |
Peak input current (INA+, INA–, INB+, INB–) | -50 | 50 | mA | |
Peak RF input power (INA+, INA–, INB+, INB–) | Single-ended with ZS-SE = 50 Ω or differential with ZS-DIFF = 100 Ω | 16.4 | dBm | |
Peak total input current (sum of absolute value of all currents forced in or out, not including power supply current) | 100 | mA | ||
Operating junction temperature, Tj | 150 | °C | ||
Storage temperature, Tstg | -65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ± 2500 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ± 1000 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
VDD | Supply Voltage Range | VA19, Analog 1.9V supply(2) | 1.8 | 1.9 | 2.0 | V |
VA11, Analog 1.1V supply(2) | 1.05 | 1.1 | 1.15 | V | ||
VD11, Digital 1.1V supply(3) | 1.05 | 1.1 | 1.15 | V | ||
VCMI | Input common mode voltage | INA+, INA–, INB+, INB–(2) | -50 | 0 | 100 | mV |
CLK+, CLK–, SYSREF+, SYSREF–(2)(4) | 0.0 | 0.3 | 0.55 | V | ||
TMSTP+, TMSTP–(2)(5) | 0.0 | 0.3 | 0.55 | V | ||
VID | Input voltage, peak-to-peak differential | CLK+ to CLK–, SYSREF+ to SYSREF–, TMSTP+ to TMSTP– | 0.4 | 1.0 | 2.0 | VPP-DIFF |
INA+ to INA–, INB+ to INB– | 1.0(6) | VPP-DIFF | ||||
VIH | High level input voltage | CALTRIG, NCOA0, NCOA1, NCOB0, NCOB1, PD, SCLK, SCS, SDI, SYNCSE(2) | 0.7 | V | ||
VIL | Low level input voltage | CALTRIG, NCOA0, NCOA1, NCOB0, NCOB1, PD, SCLK, SCS, SDI, SYNCSE(2) | 0.45 | V | ||
IC_TD | Temperature diode input current | TDIODE+ to TDIODE– | 100 | µA | ||
CL | BG max load capacitance | 50 | pF | |||
IO | BG max output current | 100 | µA | |||
DC | Input clock duty cycle | 30 | 50 | 70 | % | |
TA | Operating free-air temperature | -40 | 85 | ºC | ||
Tj | Operating junction temperature | 105(1)(7) | ºC |
THERMAL METRIC(1) | ADC12DJ3200 | UNIT | |
---|---|---|---|
AAV (FCBGA) | |||
144 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 25.3 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 1.1 | °C/W |
RθJB | Junction-to-board thermal resistance | 8.2 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.1 | °C/W |
ψJB | Junction-to-board characterization parameter | 8.2 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | n/a | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
DC ACCURACY | |||||||
Resolution | Resolution with no missing codes | 12 | bits | ||||
DNL | Differential nonlinearity | ±0.3 | LSB | ||||
INL | Integral nonlinearity | ±2.5 | LSB | ||||
ANALOG INPUTS (INA+, INA–, INB+, INB–) | |||||||
VOFF | Offset Error | Default full-scale voltage, OS_CAL disabled | ±0.6 | mV | |||
VOFF_ADJ | Input offset voltage adjustment range | Available offset correction range (see OS_CAL or OADJ_x_INx) | ±55 | mV | |||
VOFF_DRIFT | Offset Drift | Foreground calibration at nominal temperature only | 23 | µV/°C | |||
Foreground calibration at each temperature | 0 | µV/°C | |||||
VIN_FSR | Analog differential input full scale range | Default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000) | 750 | 800 | 850 | mVPP | |
Maximum full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xFFFF) | 1000 | 1040 | mVPP | ||||
Minimum full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0x2000) | 480 | 500 | mVPP | ||||
VIN_FSR_DRIFT | Analog differential input full scale range drift | Default FS_RANGE_A and FS_RANGE_B setting, foreground calibration at nominal temperature only, inputs driven by 50-Ω source, includes effect of RIN drift | -0.01 | %/°C | |||
Default FS_RANGE_A and FS_RANGE_B setting, foreground calibration at each temperature, inputs driven by 50-Ω source, includes effect of RIN drift | 0.03 | %/°C | |||||
VIN_FSR_MATCH | Analog differential input full scale range matching | Matching between INA+/INA– and INB+/INB–, default setting, dual channel mode | 0.625 | % | |||
RIN | Single-ended input resistance to AGND | Each input terminal is terminated to AGND, measured at TA = 25°C | 48 | 50 | 52 | Ω | |
RIN_TEMPCO | Input termination linear temperature coefficient | 17.6 | mΩ/°C | ||||
CIN | Single-ended input capacitance | Single channel mode at DC | 0.4 | pF | |||
Dual channel mode at DC | 0.4 | pF | |||||
TEMPERATURE DIODE CHARACTERISTICS (TDIODE+, TDIODE–) | |||||||
ΔVBE | Temperature diode voltage slope | Forced forward current of 100 µA. Offset voltage (approx. 0.792 V at 0°C) varies with process and must be measured for each part. Offset measurement should be done with the device unpowered or with the PD pin asserted to minimize device self-heating. PD pin should be asserted only long enough to take the offset measurement. | -1.6 | mV/°C | |||
BANDGAP VOLTAGE OUTPUT (BG) | |||||||
VBG | Reference output voltage | IL ≤ 100 µA | 1.1 | V | |||
VBG_DRIFT | Reference output temperature drift | IL ≤ 100 µA | -64 | µV/°C | |||
CLOCK INPUTS (CLK+, CLK–, SYSREF+, SYSREF–, TMSTP+, TMSTP–) | |||||||
ZT | Internal termination | Differential termination with DEVCLK_LVPECL_EN = 0, SYSREF_LVPECL_EN = 0 and TMSTP_LVPECL_EN = 0 | 110 | Ω | |||
Single ended termination to GND (per pin) with DEVCLK_LVPECL_EN = 0, SYSREF_LVPECL_EN = 0 and TMSTP_LVPECL_EN = 0 | 55 | Ω | |||||
VCM | Input common mode voltage, self-biased | Self-biasing common mode voltage for CLK+/– when AC coupled (DEVCLK_LVPECL_EN must be set to 0) | 0.26 | V | |||
Self-biasing common mode voltage for SYSREF+/– when AC coupled (SYSREF_LVPECL_EN must be set to 0) and with receiver enabled (SYSREF_RECV_EN = 1). | 0.29 | V | |||||
Self-biasing common mode voltage for SYSREF+/– when AC coupled (SYSREF_LVPECL_EN must be set to 0) and with receiver disabled (SYSREF_RECV_EN = 0). | VA11 | V | |||||
CL_DIFF | Differential input capacitance | Between positive and negative differential input pins | 0.1 | pF | |||
CL_SE | Single-ended input capacitance | Each input to ground | 0.5 | pF | |||
SERDES OUTPUTS (DA0+/DA0–...DA7+/DA7–, DB0+/DB0–...DB7+/DB7–) | |||||||
VOD | Differential output voltage, peak-to-peak | 100-Ω load | 550 | 600 | 650 | mVPP-DIFF | |
VCM | Output common mode voltage | AC coupled | VD11/2 | V | |||
ZDIFF | Differential output impedance | 100 | Ω | ||||
CMOS INTERFACE: SCLK, SDI, SDO, SCS, PD, NCOA0, NCOA1, NCOB0, NCOB1, CALSTAT, CALTRIG, ORA0, ORA1, ORB0, ORB1, SYNCSE | |||||||
IIH | High level input current | –40 | 40 | µA | |||
IIL | Low level input current | –40 | 40 | µA | |||
CI | Input capacitance | 2 | pF | ||||
VOH | High level output voltage | ILOAD = –400 µA | 1.65 | V | |||
VOL | Low level output voltage | ILOAD = 400 µA | 150 | mV |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
IVA19 | 1.9-V analog supply current | Power mode 1: Single channel mode, JMODE 1 (16 lanes, DDC bypassed), foreground calibration | 897 | mA | ||
IVA11 | 1.1-V analog supply current | 491 | mA | |||
IVD11 | 1.1-V digital supply current | 640 | mA | |||
PDIS | Power dissipation | 3.0 | W | |||
IVA19 | 1.9-V analog supply current | Power mode 2: Single channel mode, JMODE 0 (8 lanes, DDC bypassed), foreground calibration | 875 | 950 | mA | |
IVA11 | 1.1-V analog supply current | 515 | 600 | mA | ||
IVD11 | 1.1-V digital supply current | 615 | 750 | mA | ||
PDIS | Power dissipation | 2.9 | 3.5 | W | ||
IVA19 | 1.9-V analog supply current | Power mode 3: Single channel mode, JMODE 1 (16 lanes, DDC bypassed), background calibration | 1181 | mA | ||
IVA11 | 1.1-V analog supply current | 595 | mA | |||
IVD11 | 1.1-V digital supply current | 653 | mA | |||
PDIS | Power dissipation | 3.6 | W | |||
IVA19 | 1.9-V analog supply current | Power mode 4: Dual channel mode, JMODE 3 (16 lanes, DDC bypassed), background calibration | 1260 | mA | ||
IVA11 | 1.1-V analog supply current | 594 | mA | |||
IVD11 | 1.1-V digital supply current | 636 | mA | |||
PDIS | Power dissipation | 3.8 | W | |||
IVA19 | 1.9-V analog supply current | Power mode 5: Dual channel mode, JMODE 11 (8 lanes, 4x decimation), foreground calibration | 964 | mA | ||
IVA11 | 1.1-V analog supply current | 493 | mA | |||
IVD11 | 1.1-V digital supply current | 802 | mA | |||
PDIS | Power dissipation | 3.3 | W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
FPBW | Full-power input bandwidth (–3 dB)(1) | Foreground calibration | 8.1 | GHz | ||
Background calibration | 8.1 | |||||
XTALK | Channel-to-channel Crosstalk | Aggressor = 400 MHz, – 1 dBFS | –93 | dB | ||
Aggressor = 3 GHz, – 1 dBFS | –70 | |||||
Aggressor = 6 GHz, – 1 dBFS | –63 | |||||
CER | Code error rate | 10–18 | errors/sample | |||
NOISEDC | DC input noise standard deviation | No input, foreground calibration, excludes DC offset, includes fixed interleaving spur (Fs/2 spur) | 2 | LSB | ||
NSD | Noise spectral density, no input signal, excludes fixed interleaving spur (Fs/2 spur) | Maximum full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xFFFF) setting, foreground calibration | -151.8 | dBFS/Hz | ||
Default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000) setting, foreground calibration | -150.2 | |||||
NF | Noise figure, no input, ZS = 100 Ω | Maximum full-scale voltage (FS_RANGE_A = 0xFFFF) setting, foreground calibration | 23.5 | dB | ||
Default full-scale voltage (FS_RANGE_A = 0xA000) setting, foreground calibration | 22.8 | |||||
SNR | Signal to noise ratio, large signal, excluding DC, HD2 to HD9 and interleaving spurs | fIN = 347 MHz, AIN = –1 dBFS | 56.6 | dBFS | ||
fIN = 347 MHz, AIN = –1 dBFS, maximum FS_RANGE_A and FS_RANGE_B setting, foreground calibration | 57.6 | |||||
fIN = 997 MHz, AIN = –1 dBFS | 56.3 | |||||
fIN = 2482 MHz, AIN = –1 dBFS | 52 | 55.2 | ||||
fIN = 2482 MHz, AIN = –1 dBFS, maximum FS_RANGE_A and FS_RANGE_B setting, foreground calibration | 56.1 | |||||
fIN = 4997 MHz, AIN = –1 dBFS | 52.6 | |||||
fIN = 6397 MHz, AIN = –1 dBFS | 51.3 | |||||
fIN = 8197 MHz, AIN = –1 dBFS | 49.8 | |||||
SNR | Signal to noise ratio, small signal, excluding DC, HD2 to HD9 and interleaving spurs | fIN = 347 MHz, AIN = –16 dBFS | 57.4 | dBFS | ||
fIN = 997 MHz, AIN = –16 dBFS | 57.5 | |||||
fIN = 2482 MHz, AIN = –16 dBFS | 57.4 | |||||
fIN = 4997 MHz, AIN = –16 dBFS | 57.1 | |||||
fIN = 6397 MHz, AIN = –16 dBFS | 57.3 | |||||
fIN = 8197 MHz, AIN = –16 dBFS | 56.9 | |||||
SINAD | Signal to noise and distortion ratio, large signal, excluding DC and FS/2 fixed spurs | fIN = 347 MHz, AIN = –1 dBFS | 56.0 | dBFS | ||
fIN = 997 MHz, AIN = –1 dBFS | 55.7 | |||||
fIN = 2482 MHz, AIN = –1 dBFS | 51 | 54.6 | ||||
fIN = 4997 MHz, AIN = –1 dBFS | 50.3 | |||||
fIN = 6397 MHz, AIN = –1 dBFS | 48.9 | |||||
fIN = 8197 MHz, AIN = –1 dBFS | 47.4 | |||||
ENOB | Effective number of bits, large signal, excluding DC and FS/2 fixed spurs | fIN = 347 MHz, AIN = –1 dBFS | 9.0 | bits | ||
fIN = 997 MHz, AIN = –1 dBFS | 9.0 | |||||
fIN = 2482 MHz, AIN = –1 dBFS | 8.2 | 8.8 | ||||
fIN = 4997 MHz, AIN = –1 dBFS | 8.1 | |||||
fIN = 6397 MHz, AIN = –1 dBFS | 7.8 | |||||
fIN = 8197 MHz, AIN = –1 dBFS | 7.6 | |||||
SFDR | Spurious free dynamic range, large signal, excluding DC and FS/2 fixed spurs | fIN = 347 MHz, AIN = –1 dBFS | 67 | dBFS | ||
fIN = 347 MHz, AIN = –1 dBFS, maximum FS_RANGE_A and FS_RANGE_B setting, foreground calibration | 67 | |||||
fIN = 997 MHz, AIN = –1 dBFS | 69 | |||||
fIN = 2482 MHz, AIN = –1 dBFS | 60 | 66 | ||||
fIN = 2482 MHz, AIN = –1 dBFS, maximum FS_RANGE_A and FS_RANGE_B setting, foreground calibration | 63 | |||||
fIN = 4997 MHz, AIN = –1 dBFS | 56 | |||||
fIN = 6397 MHz, AIN = –1 dBFS | 55 | |||||
fIN = 8197 MHz, AIN = –1 dBFS | 52 | |||||
SFDR | Spurious free dynamic range, small signal, excluding DC and FS/2 fixed spurs | fIN = 347 MHz, AIN = –16 dBFS | 73 | dBFS | ||
fIN = 997 MHz, AIN = –16 dBFS | 72 | |||||
fIN = 2482 MHz, AIN = –16 dBFS | 72 | |||||
fIN = 4997 MHz, AIN = –16 dBFS | 72 | |||||
fIN = 6397 MHz, AIN = –16 dBFS | 72 | |||||
fIN = 8197 MHz, AIN = –16 dBFS | 72 | |||||
FS/2 | FS/2 fixed interleaving spur, independent of input signal | No input | –75 | –55 | dBFS | |
HD2 | 2nd order harmonic | fIN = 347 MHz, AIN = –1 dBFS | –73 | dBFS | ||
fIN = 347 MHz, AIN = –1 dBFS, maximum FS_RANGE_A and FS_RANGE_B setting, foreground calibration | –72 | |||||
fIN = 997 MHz, AIN = –1 dBFS | –72 | |||||
fIN = 2482 MHz, AIN = –1 dBFS | –67 | –60 | ||||
fIN = 2482 MHz, AIN = –1 dBFS, maximum FS_RANGE_A and FS_RANGE_B setting, foreground calibration | –66 | |||||
fIN = 4997 MHz, AIN = –1 dBFS | –58 | |||||
fIN = 6397 MHz, AIN = –1 dBFS | –57 | |||||
fIN = 8197 MHz, AIN = –1 dBFS | –58 | |||||
HD3 | 3rd order harmonic | fIN = 347 MHz, AIN = –1 dBFS | –70 | dBFS | ||
fIN = 347 MHz, AIN = –1 dBFS, maximum FS_RANGE_A and FS_RANGE_B setting, foreground calibration | –68 | |||||
fIN = 997 MHz, AIN = –1 dBFS | –72 | |||||
fIN = 2482 MHz, AIN = –1 dBFS | –69 | –60 | ||||
fIN = 2482 MHz, AIN = –1 dBFS, maximum FS_RANGE_A and FS_RANGE_B setting, foreground calibration | –63 | |||||
fIN = 4997 MHz, AIN = –1 dBFS | –57 | |||||
fIN = 6397 MHz, AIN = –1 dBFS | –55 | |||||
fIN = 8197 MHz, AIN = –1 dBFS | –52 | |||||
FS/2-FIN | FS/2-FIN interleaving spur, signal dependent | fIN = 347 MHz, AIN = –1 dBFS | –69 | dBFS | ||
fIN = 997 MHz, AIN = –1 dBFS | –70 | |||||
fIN = 2482 MHz, AIN = –1 dBFS | –70 | –60 | ||||
fIN = 4997 MHz, AIN = –1 dBFS | –67 | |||||
fIN = 6397 MHz, AIN = –1 dBFS | –63 | |||||
fIN = 8197 MHz, AIN = –1 dBFS | –63 | |||||
SPUR | Worst harmonic 4th order or higher | fIN = 347 MHz, AIN = –1 dBFS | –72 | dBFS | ||
fIN = 997 MHz, AIN = –1 dBFS | –72 | |||||
fIN = 2482 MHz, AIN = –1 dBFS | –73 | –65 | ||||
fIN = 4997 MHz, AIN = –1 dBFS | –70 | |||||
fIN = 6397 MHz, AIN = –1 dBFS | –69 | |||||
fIN = 8197 MHz, AIN = –1 dBFS | –67 | |||||
IMD3 | 3rd order intermodulation | fIN = 347 MHz ± 5 MHz,
AIN = –7 dBFS per tone |
–81 | dBFS | ||
fIN = 997 MHz ± 5 MHz,
AIN = –7 dBFS per tone |
–78 | |||||
fIN = 2482 MHz ± 5 MHz,
AIN = –7 dBFS per tone |
–73 | |||||
fIN = 4997 MHz ± 5 MHz,
AIN = –7 dBFS per tone |
–65 | |||||
fIN = 6397 MHz ± 5 MHz,
AIN = –7 dBFS per tone |
–56 | |||||
fIN = 8197 MHz ± 5 MHz,
AIN = –7 dBFS per tone |
–46 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
FPBW | Full-power input bandwidth (–3 dB)(1) | Foreground calibration | 7.9 | GHz | ||
Background calibration | 7.9 | |||||
CER | Code error rate | 10–18 | errors/sample | |||
NOISEDC | DC input noise standard deviation | No input, foreground calibration, excludes DC offset, includes fixed interleaving spurs (Fs/2 and Fs/4 spurs) | 3.5 | LSB | ||
NSD | Noise spectral density, no input signal, excludes fixed interleaving spurs (Fs/2 and Fs/4 spur) | Maximum full-scale voltage (FS_RANGE_A = 0xFFFF) setting, foreground calibration | -154.6 | dBFS/Hz | ||
Default full-scale voltage (FS_RANGE_A = 0xA000) setting, foreground calibration | -153.1 | |||||
NF | Noise figure, no input, ZS = 100 Ω | Maximum full-scale voltage (FS_RANGE_A = 0xFFFF) setting, foreground calibration | 20.7 | dB | ||
Default full-scale voltage (FS_RANGE_A = 0xA000) setting, foreground calibration | 19.9 | |||||
SNR | Signal to noise ratio, large signal, excluding DC, HD2 to HD9 and interleaving spurs | fIN = 347 MHz, AIN = –1 dBFS | 56.6 | dBFS | ||
fIN = 347 MHz, AIN = –1 dBFS, maximum FS_RANGE_A setting, foreground calibration | 57.5 | |||||
fIN = 997 MHz, AIN = –1 dBFS | 56.3 | |||||
fIN = 2482 MHz, AIN = –1 dBFS | 52 | 55.3 | ||||
fIN = 2482 MHz, AIN = –1 dBFS, maximum FS_RANGE_A setting, foreground calibration | 56.1 | |||||
fIN = 4997 MHz, AIN = –1 dBFS | 53.0 | |||||
fIN = 6397 MHz, AIN = –1 dBFS | 51.6 | |||||
fIN = 8197 MHz, AIN = –1 dBFS | 50.0 | |||||
SNR | Signal to noise ratio, small signal, excluding DC, HD2 to HD9 and interleaving spurs | fIN = 347 MHz, AIN = –16 dBFS | 57.4 | dBFS | ||
fIN = 997 MHz, AIN = –16 dBFS | 57.6 | |||||
fIN = 2482 MHz, AIN = –16 dBFS | 57.4 | |||||
fIN = 4997 MHz, AIN = –16 dBFS | 57.3 | |||||
fIN = 6397 MHz, AIN = –16 dBFS | 57.4 | |||||
fIN = 8197 MHz, AIN = –16 dBFS | 57.0 | |||||
SINAD | Signal to noise and distortion ratio, large signal, excluding DC and FS/2 fixed spurs | fIN = 347 MHz, AIN = –1 dBFS | 52.7 | dBFS | ||
fIN = 997 MHz, AIN = –1 dBFS | 52.4 | |||||
fIN = 2482 MHz, AIN = –1 dBFS | 48 | 52.1 | ||||
fIN = 4997 MHz, AIN = –1 dBFS | 47.5 | |||||
fIN = 6397 MHz, AIN = –1 dBFS | 46.6 | |||||
fIN = 8197 MHz, AIN = –1 dBFS | 47.7 | |||||
ENOB | Effective number of bits, large signal, excluding DC and FS/2 fixed spurs | fIN = 347 MHz, AIN = –1 dBFS | 8.6 | Bits | ||
fIN = 997 MHz, AIN = –1 dBFS | 8.5 | |||||
fIN = 2482 MHz, AIN = –1 dBFS | 7.7 | 8.4 | ||||
fIN = 4997 MHz, AIN = –1 dBFS | 7.7 | |||||
fIN = 6397 MHz, AIN = –1 dBFS | 7.5 | |||||
fIN = 8197 MHz, AIN = –1 dBFS | 7.6 | |||||
SFDR | Spurious free dynamic range, large signal, excluding DC, FS/4 and FS/2 fixed spurs | fIN = 347 MHz, AIN = –1 dBFS | 67 | dBFS | ||
fIN = 347 MHz, AIN = –1 dBFS, maximum FS_RANGE_A setting, foreground calibration | 64 | |||||
fIN = 997 MHz, AIN = –1 dBFS | 63 | |||||
fIN = 2482 MHz, AIN = –1 dBFS | 50 | 58 | ||||
fIN = 2482 MHz, AIN = –1 dBFS, maximum FS_RANGE_A setting, foreground calibration | 55 | |||||
fIN = 4997 MHz, AIN = –1 dBFS | 51 | |||||
fIN = 6397 MHz, AIN = –1 dBFS | 50 | |||||
fIN = 8197 MHz, AIN = –1 dBFS | 48 | |||||
SFDR | Spurious free dynamic range, small signal, excluding DC, FS/4 and FS/2 fixed spurs | fIN = 347 MHz, AIN = –16 dBFS | 75 | dBFS | ||
fIN = 997 MHz, AIN = –16 dBFS | 73 | |||||
fIN = 2482 MHz, AIN = –16 dBFS | 72 | |||||
fIN = 4997 MHz, AIN = –16 dBFS | 66 | |||||
fIN = 6397 MHz, AIN = –16 dBFS | 65 | |||||
fIN = 8197 MHz, AIN = –16 dBFS | 63 | |||||
FS/2 | FS/2 fixed interleaving spur, independent of input signal | No input, OS_CAL disabled. Spur can be improved by running OS_CAL. | –56 | dBFS | ||
FS/4 | FS/4 fixed interleaving spur, independent of input signal | No input | –65 | –55 | dBFS | |
HD2 | 2nd order harmonic | fIN = 347 MHz, AIN = –1 dBFS | –73 | dBFS | ||
fIN = 347 MHz, AIN = –1 dBFS, maximum FS_RANGE_A setting, foreground calibration | –76 | |||||
fIN = 997 MHz, AIN = –1 dBFS | –74 | |||||
fIN = 2482 MHz, AIN = –1 dBFS | –68 | –60 | ||||
fIN = 2482 MHz, AIN = –1 dBFS, maximum FS_RANGE_A setting, foreground calibration | –72 | |||||
fIN = 4997 MHz, AIN = –1 dBFS | –62 | |||||
fIN = 6397 MHz, AIN = –1 dBFS | –62 | |||||
fIN = 8197 MHz, AIN = –1 dBFS | –61 | |||||
HD3 | 3rd order harmonic | fIN = 347 MHz, AIN = –1 dBFS | –70 | dBFS | ||
fIN = 347 MHz, AIN = –1 dBFS, maximum FS_RANGE_A setting, foreground calibration | –68 | |||||
fIN = 997 MHz, AIN = –1 dBFS | –68 | |||||
fIN = 2482 MHz, AIN = –1 dBFS | –69 | –60 | ||||
fIN = 2482 MHz, AIN = –1 dBFS, maximum FS_RANGE_A setting, foreground calibration | –64 | |||||
fIN = 4997 MHz, AIN = –1 dBFS | –59 | |||||
fIN = 6397 MHz, AIN = –1 dBFS | –58 | |||||
fIN = 8197 MHz, AIN = –1 dBFS | –55 | |||||
FS/2-FIN | FS/2-FIN interleaving spur, signal dependent | fIN = 347 MHz, AIN = –1 dBFS | –68 | dBFS | ||
fIN = 997 MHz, AIN = –1 dBFS | –63 | |||||
fIN = 2482 MHz, AIN = –1 dBFS | –58 | –50 | ||||
fIN = 4997 MHz, AIN = –1 dBFS | –51 | |||||
fIN = 6397 MHz, AIN = –1 dBFS | –50 | |||||
fIN = 8197 MHz, AIN = –1 dBFS | –48 | |||||
FS/4±FIN | FS/4±FIN interleaving spurs, signal dependent | fIN = 347 MHz, AIN = –1 dBFS | –74 | dBFS | ||
fIN = 997 MHz, AIN = –1 dBFS | –69 | |||||
fIN = 2482 MHz, AIN = –1 dBFS | –70 | –60 | ||||
fIN = 4997 MHz, AIN = –1 dBFS | –66 | |||||
fIN = 6397 MHz, AIN = –1 dBFS | –63 | |||||
fIN = 8197 MHz, AIN = –1 dBFS | –61 | |||||
SPUR | Worst harmonic 4th order or higher | fIN = 347 MHz, AIN = –1 dBFS | –73 | dBFS | ||
fIN = 997 MHz, AIN = –1 dBFS | –73 | |||||
fIN = 2482 MHz, AIN = –1 dBFS | –75 | –65 | ||||
fIN = 4997 MHz, AIN = –1 dBFS | –69 | |||||
fIN = 6397 MHz, AIN = –1 dBFS | –69 | |||||
fIN = 8197 MHz, AIN = –1 dBFS | –63 | |||||
IMD3 | 3rd order intermodulation | fIN = 347 MHz ± 5 MHz,
AIN = –7 dBFS per tone |
–80 | dBFS | ||
fIN = 997 MHz ± 5 MHz,
AIN = –7 dBFS per tone |
–75 | |||||
fIN = 2482 MHz ± 5 MHz,
AIN = –7 dBFS per tone |
–72 | |||||
fIN = 4997 MHz ± 5 MHz,
AIN = –7 dBFS per tone |
–63 | |||||
fIN = 6397 MHz ± 5 MHz,
AIN = –7 dBFS per tone |
–65 | |||||
fIN = 8197 MHz ± 5 MHz,
AIN = –7 dBFS per tone |
–50 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
DEVICE (SAMPLING) CLOCK (CLK+, CLK–) | ||||||
fCLK | Input clock frequency (CLK+, CLK–), both single channel and dual channel modes(1) | 800 | 3200 | MHz | ||
SYSREF (SYSREF+, SYSREF–) | ||||||
tINV(SYSREF) | Width of invalid SYSREF capture region of CLK+/– period, indicating setup or hold time violation, as measured by SYSREF_POS status register(2) | 48 | ps | |||
tINV(TEMP) | Drift of invalid SYSREF capture region over temperature, positive number indicates a shift toward MSB of SYSREF_POS register | 0 | ps/°C | |||
tINV(VA11) | Drift of invalid SYSREF capture region over VA11 supply voltage, positive number indicates a shift toward MSB of SYSREF_POS register | 0.36 | ps/mV | |||
tSTEP(SP) | Delay of SYSREF_POS LSB | SYSREF_ZOOM = 0 | 77 | ps | ||
SYSREF_ZOOM = 1 | 24 | ps | ||||
t(PH_SYS) | Minimum SYSREF+/– assertion duration after SYSREF+/– rising edge event | 4 | ns | |||
t(PL_SYS) | Minimum SYSREF+/– deassertion duration after SYSREF+/– falling edge event | 1 | ns | |||
JESD204B SYNC TIMING (SYNCSE OR TMSTP+/–) | ||||||
tH(SYNCSE) | Minimum hold time from multi-frame boundary (SYSREF rising edge captured high) to de-assertion of JESD204B SYNC signal (SYNCSE if SYNC_SEL = 0 or TMSTP+/– if SYNC_SEL = 1) for NCO synchronization (NCO_SYNC_ILA = 1) | JMODE = 0, 2, 4, 6, 10, 13 or 15 | 21 | tCLK cycles | ||
JMODE = 1, 3, 5, 7, 9, 11, 14 or 16 | 17 | |||||
JMODE = 12, 17 or 18 | 9 | |||||
tSU(SYNCSE) | Minimum setup time from de-assertion of JESD204B SYNC signal (SYNCSE if SYNC_SEL = 0 or TMSTP+/– if SYNC_SEL = 1) to multi-frame boundary (SYSREF rising edge captured high) for NCO synchronization (NCO_SYNC_ILA = 1) | JMODE = 0, 2, 4, 6, 10, 13 or 15 | –2 | tCLK cycles | ||
JMODE = 1, 3, 5, 7, 9, 11, 14 or 16 | 2 | |||||
JMODE = 12, 17 or 18 | 10 | |||||
t(SYNCSE) | SYNCSE minimum assertion time to trigger link resynchronization | 4 | Frames | |||
SERIAL PROGRAMMING INTERFACE (SCLK, SDI, SCS) | ||||||
fCLK(SCLK) | Maximum serial clock frequency | 15.625 | MHz | |||
t(PH) | Minimum serial clock high value pulse width | 32 | ns | |||
t(PL) | Minimum serial clock low value pulse width | 32 | ns | |||
tSU(SCS) | Minimum setup time from SCS to rising edge of SCLK | 30 | ns | |||
tH(SCS) | Minimum hold time from rising edge of SCLK to SCS | 3 | ns | |||
tSU(SDI) | Minimum setup time from SDI to rising edge of SCLK | 30 | ns | |||
tH(SDI) | Minimum hold time from rising edge of SCLK to SDI | 3 | ns |