SLVSDC2C February 2016 – August 2021 TPS65981
PRODUCTION DATA
The VIN_3V3 voltage is connected to VRSTZ_3V3 by a single FET switch (S2 in Figure 9-40).
The enabling of the switch is controlled by the core digital circuitry and the conditions are programmable. A supervisor circuit monitors the voltage at VRSTZ_3V3 for an under-voltage condition and sets the external indicator RESETZ. The RESETZ pin is active low (low when an under-voltage condition occurs). The RESETZ output is also asserted when the MRESET input is asserted. The MRESET input is active-high by default, but is configurable to be active low. Figure 8-1 shows the RESETZ timing with MRESET set to active high. When VRSTZ_3V3 is disabled in application code, a resistance of RPDOUT_3V3 pulls down on the pin.