SLVSDD0B May   2016  – September 2017 TPS22975

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics—VBIAS = 5 V
    6. 7.6 Electrical Characteristics—VBIAS = 2.5 V
    7. 7.7 Switching Characteristics
    8. 7.8 Typical DC Characteristics
    9. 7.9 Typical AC Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Adjustable Rise Time
      2. 9.3.2 Quick-Output Discharge (QOD) (Optional)
      3. 9.3.3 Thermal Shutdown
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 ON and OFF Control
      2. 10.1.2 Input Capacitor (CIN) (Optional)
      3. 10.1.3 Output Capacitor (CL) (Optional)
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Inrush Current
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Thermal Considerations
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Developmental Support
    2. 13.2 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Community Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

12 Layout

12.1 Layout Guidelines

For best performance, all traces must be as short as possible. To be most effective, the input and output capacitors must be placed close to the device to minimize the effects that parasitic trace inductances may have on normal operation. Using wide traces for VIN, VOUT, and GND helps minimize the parasitic electrical effects along with minimizing the case to ambient thermal impedance. The CT trace must be as short as possible to reduce parasitic capacitance.

12.2 Layout Example

TPS22975 lay_exp_slvsci3.gif Figure 34. Layout Recommendation

12.3 Thermal Considerations

The maximum IC junction temperature must be restricted to 125°C under normal operating conditions. To calculate the maximum allowable dissipation, PD(max) , for a given ambient temperature, use Equation 5 as a guideline.

Equation 5. TPS22975 eq2_lvsbh4.gif

where

  • PD(max) is the maximum allowable power dissipation
  • TJ(max) is the maximum allowable junction temperature (125°C for the TPS22975)
  • TA is the ambient temperature of the device
  • ΘJA is the junction to air thermal impedance. See the Thermal Information section. This parameter is highly dependent upon board layout.

In Figure 34, notice that the thermal vias are located under the exposed thermal pad of the device. This allows for thermal diffusion away from the device.