SLVSDE7D November   2016  – December 2023 TPS22976

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
    1.     Pin Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics (VBIAS = 5V)
    6. 6.6  Electrical Characteristics (VBIAS = 2.5V)
    7. 6.7  Switching Characteristics (TPS22976)
    8. 6.8  Switching Characteristics (TPS22976A)
    9. 6.9  Switching Characteristics (TPS22976N)
    10. 6.10 Typical DC Characteristics
    11. 6.11 Typical AC Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 ON and OFF Control
      2. 8.3.2 Input Capacitor (Optional)
      3. 8.3.3 Output Capacitor (Optional)
      4. 8.3.4 Quick Output Discharge (QOD) (Not Present in TPS22976N)
      5. 8.3.5 Thermal Shutdown
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Parallel Configuration
      2. 9.1.2 Standby Power Reduction
      3. 9.1.3 Power Supply Sequencing without GPIO Input
      4. 9.1.4 Reverse Current Blocking
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inrush Current
        2. 9.2.2.2 Adjustable Rise Time
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
      3. 9.4.3 Power Dissipation
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Developmental Support
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.3.3 Output Capacitor (Optional)

Due to the integrated body diode in the NMOS switch, a CIN greater than CL is highly recommended. A CL greater than CIN can cause VOUT to exceed VIN when the system supply is removed. This could result in current flow through the body diode from VOUT to VIN. A CIN to CL ratio of 10 to 1 is recommended for minimizing VIN dip caused by inrush currents during startup, however a 10 to 1 ratio for capacitance is not required for proper functionality of the device. A ratio smaller than 10 to 1 (such as 1 to 1) could cause slightly more VIN dip upon turnon due to inrush currents. This can be mitigated by increasing the capacitance on the CT pin for a longer rise time (see the Adjustable Rise Time section).