SLVSDG5C March   2016  – August 2020 TPD3S014-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings—AEC Specification
    3. 6.3 ESD Ratings—IEC Specification
    4. 6.4 ESD Ratings—ISO Specification
    5. 6.5 Recommended Operating Conditions
    6. 6.6 Thermal Information
    7. 6.7 Electrical Characteristics: TJ = TA = 25°C
    8. 6.8 Electrical Characteristics: –40°C ≤ TA ≤ 105°C
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Undervoltage Lockout (UVLO)
      2. 8.3.2 Enable
      3. 8.3.3 Internal Charge Pump
      4. 8.3.4 Current Limit
      5. 8.3.5 Output Discharge
      6. 8.3.6 Input and Output Capacitance
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation With VIN < 4 V (Minimum VIN)
      2. 8.4.2 Operation With EN Control
      3. 8.4.3 Operation of Level 4 IEC 61000-4-2 ESD Protection
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Implementing Active Low Logic
      4. 9.2.4 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Power Dissipation and Junction Temperature
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

8.3.2 Enable

The logic enable input (EN) controls the power switch, bias for the charge pump, driver, and other circuits. The supply current is reduced to less than 1 µA when the TPD3S014-Q1 is disabled. The enable input is compatible with both TTL and CMOS logic levels.

The turnon and turnoff times (tON, tOFF) are composed of a delay and a rise or fall time (tR, tF). The delay times are internally controlled. The rise time is controlled by both the TPD3S014-Q1 and the external loading (especially capacitance). The TPD3S014-Q1 fall time is controlled by the loading (R and C), and the output discharge (RPD). An output load consisting of only a resistor experiences a fall time set by the TPD3S014-Q1. An output load with parallel R and C elements experiences a fall time determined by the (R × C) time constant if it is longer than the TPD3S014-Q1 tF. See Figure 8-1 and Figure 8-2 showing tR, tF, tON, and tOFF. The enable must not be left open; it may be tied to VIN.

GUID-493CD068-FAD4-44F9-9ADD-636015330D95-low.gifFigure 8-1 Power-On and Power-Off Timing
GUID-895D60B7-4EFB-403E-A9FE-12B95BA550F2-low.gifFigure 8-2 Enable Timing, Active-High Enable