SLVSDH0C December   2016  – January 2018 TPS22810

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Simplified Schematic
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical DC Characteristics
    8. 7.8 Typical AC Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 On and Off Control
      2. 9.3.2 Quick Output Discharge (QOD)
        1. 9.3.2.1 QOD when System Power is Removed
        2. 9.3.2.2 Internal QOD Considerations
      3. 9.3.3 EN/UVLO
      4. 9.3.4 Adjustable Rise Time (CT)
      5. 9.3.5 Thermal Shutdown
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 ON and OFF Control
    3. 10.3 Input Capacitor (Optional)
    4. 10.4 Output Capacitor (Optional)
    5. 10.5 Typical Application
      1. 10.5.1 Design Requirements
      2. 10.5.2 Detailed Design Procedure
        1. 10.5.2.1 Shutdown Sequencing During Unexpected Power Loss
        2. 10.5.2.2 VIN to VOUT Voltage Drop
        3. 10.5.2.3 Inrush Current
      3. 10.5.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Thermal Considerations
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Developmental Support
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Community Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

9.3.3 EN/UVLO

As an input pin, EN/UVLO controls the ON and OFF state of the internal MOSFET. In its high state, the internal MOSFET is enabled. A low on this pin turns off the internal MOSFET. High and Low levels are specified in the parametric table of the datasheet

A voltage V(EN/UVLO < V(ENF) on this pin turns off the internal FET, thus disconnecting VIN from VOUT, while voltage below V(SHUTF) takes the device into shutdown mode, with IQ less than 1 μA to ensure minimal power loss.

The EN/UVLO pin can be directly driven by a 1.8 V, 3.3 V or 5 V general purpose output pin.

The internal de-glitch delay on EN/UVLO falling edge is intentionally kept low (2.5 μs typical) for quick detection of power failure. For applications where a higher de-glitch delay on EN/UVLO is desired, or when the supply is particularly noisy, it is recommended to use an external bypass capacitor from EN/UVLO to GND.

The undervoltage lock out can be programmed by using an external resistor divider from supply VIN terminal to EN/UVLO terminal to GND as shown in Figure 18. When an undervoltage or input power fail event is detected, the internal FET is quickly turned off. If the Under-Voltage Lock-Out function is not needed, the EN/UVLO terminal must be connected to the VIN terminal. EN/UVLO terminal must not be left floating.

The device also implements internal undervoltage-lockout (UVLO) circuitry on the VIN terminal. The device disables when the VIN terminal voltage falls below internal UVLO Threshold V(UVF). The internal UVLO threshold has a hysteresis of 125 mV (5% of V(UVR)). See Figure 19 and Figure 20.

TPS22810 ConfigUVLOwithExternalResistor_SLVS.gifFigure 18. Configuring UVLO with External Resistor Network
TPS22810 Using18V33VGPIOdirectsignal_SLVSDH0.gifFigure 19. Using 1.8 V/3.3 V GPIO Signal Directly from Processor
TPS22810 DefaultUVLOthreshold_SLVSDH0.gifFigure 20. Default UVLO Threshold V(UVR) Using No Additional External Components