SLVSDM4D November   2018  – December 2019 TPS1HA08-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Simplified Schematic
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
    2. 6.1 Recommended Connections for Unused Pins
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 SNS Timing Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
      1. 9.1.1 Device Nomenclature
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Protection Mechanisms
        1. 9.3.1.1 Thermal Shutdown
        2. 9.3.1.2 Current Limit
          1. 9.3.1.2.1 Current Limit Foldback
          2. 9.3.1.2.2 Selectable Current Limit Threshold
          3. 9.3.1.2.3 Undervoltage Lockout (UVLO)
          4. 9.3.1.2.4 VBB during Short-to-Ground
        3. 9.3.1.3 Energy Limit
        4. 9.3.1.4 Voltage Transients
          1. 9.3.1.4.1 Load Dump
          2. 9.3.1.4.2 Driving Inductive and Capacitive Loads
        5. 9.3.1.5 Reverse Battery
        6. 9.3.1.6 Fault Event – Timing Diagrams
      2. 9.3.2 Diagnostic Mechanisms
        1. 9.3.2.1 VOUT Short-to-Battery and Open-Load
          1. 9.3.2.1.1 Detection With Switch Enabled
          2. 9.3.2.1.2 Detection With Switch Disabled
        2. 9.3.2.2 SNS Output
          1. 9.3.2.2.1 RSNS Value
            1. 9.3.2.2.1.1 High Accuracy Load Current Sense
            2. 9.3.2.2.1.2 SNS Output Filter
        3. 9.3.2.3 ST Pin
        4. 9.3.2.4 Fault Indication and SNS Mux
        5. 9.3.2.5 Resistor Sharing
        6. 9.3.2.6 High-Frequency, Low Duty-Cycle Current Sensing
      3. 9.3.3 Enable Watchdog
    4. 9.4 Device Functional Modes
      1. 9.4.1 Off
      2. 9.4.2 Standby
      3. 9.4.3 Diagnostic
      4. 9.4.4 Standby Delay
      5. 9.4.5 Active
      6. 9.4.6 Fault
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Ground Protection Network
      2. 10.1.2 Interface With Microcontroller
      3. 10.1.3 I/O Protection
      4. 10.1.4 Inverse Current
      5. 10.1.5 Loss of GND
      6. 10.1.6 Automotive Standards
        1. 10.1.6.1 ISO7637-2
        2. 10.1.6.2 AEC – Q100-012 Short Circuit Reliability
      7. 10.1.7 Thermal Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Thermal Considerations
        2. 10.2.2.2 Diagnostics
          1. 10.2.2.2.1 Selecting the RISNS Value
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Related Documentation
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

12.1 Layout Guidelines

To achieve optimal thermal performance, connect the exposed pad to a large copper pour. On the top PCB layer, the pour may extend beyond the pad dimensions as shown in the example below. In addition to this, it is recommended to also have a VBB plane either on one of the internal PCB layers or on the bottom layer. Vias should connect this plane to the top VBB pour.

has 6 VOUT pins. All VOUT pins must be shorted together on the PCB. Additionally, the layout should ensure that the current path is symmetrical for both sides of the device. If the path is not symmetrical, there will be some imbalance in current spreading across the power FET. This can impact accuracy of the current sense measurement.