SLVSDO6C August 2017 – June 2019 TPS1H000-Q1
PRODUCTION DATA.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
OPERATING VOLTAGE | ||||||
VVS(nom) | Nominal operating voltage | 4 | 40 | V | ||
VVS(uvr) | Undervoltage restart | VVS rising | 3.5 | 3.7 | 4 | V |
VVS(uvf) | Undervoltage shutdown | VVS falling | 3 | 3.2 | 3.4 | V |
V(uv,hys) | Undervoltage shutdown, hysteresis | 0.5 | V | |||
OPERATING CURRENT | ||||||
I(op) | Nominal operating current | VVS = 13.5 V, VIN = 5 V, VDIAG_EN = 0 V, IOUT = 0.1 A, ICL = 0.5 A. | 5 | mA | ||
I(off) | Standby current | VVS = 13.5 V, VIN = VDIAG_EN = VCL = VOUT = 0 V, TJ = 25 °C | 0.5 | µA | ||
VVS = 13.5 V, VIN = VDIAG_EN = VCL = VOUT = 0 V, TJ = 125 °C | 3 | |||||
I(off,diag) | Standby current with diagnostics enabled | VVS = 13.5 V, VIN = 0 V, VDIAG_EN = 5 V | 3 | mA | ||
t(off,deg) | Standby-mode deglitch time(1) | IN from high to low, if deglitch time≥ t(off,deg), the device enters into standby mode. | 12.5 | ms | ||
Ilkg(out) | Output leakage current in off-state | VVS = 13.5 V, VIN = VDIAG_EN = VOUT = 0 V | 3 | µA | ||
POWER STAGE | ||||||
rDS(on) | On-state resistance | VVS ≥ 3.5 V, TJ = 25°C | 1000 | mΩ | ||
VVS ≥ 3.5 V, TJ = 150°C | 2000 | |||||
ICL(int) | Internal current limit | CL pin connected to GND | 1 | 1.8 | A | |
ICL(TSD) | Current-limit value percentage during thermal shutdown | 60% | ||||
VDS(clamp) | Drain−to−source voltage internally clamped | 45 | 65 | V | ||
OUTPUT DIODE CHARACTERISTICS | ||||||
VF | Drain−to-source diode voltage | IN = 0, IOUT = −0.15 A | 0.3 | 0.7 | 1 | V |
IR(1) | Continuous reverse current from source to drain during a short-to-battery condition(1) | t < 60 s, VIN= 0 V, TJ = 25°C. | 1 | A | ||
IR(2) | Continuous reverse current from source to drain during a reverse-polarity condition(1) | t < 60 s, VIN= 0 V, TJ = 25°C. GND pin 1-kΩ resistor in parallel with diode. | 1 | A | ||
LOGIC INPUT (IN, DIAG_EN) | ||||||
VIH | Logic high-level voltage | 2 | V | |||
VIL | Logic low-level voltage | 0.8 | V | |||
Rpd,in | Logic-pin pulldown resistor | IN. VIN = 5 V | 150 | 400 | kΩ | |
DIAG_EN. VVS = VDIAG_EN = 5 V | 350 | 850 | ||||
DIAGNOSTICS | ||||||
Ilkg(loss,GND) | Loss of ground output leakage current | 100 | µA | |||
td(ol,on) | Open-load deglitch time in on-state | VIN = 5 V, VDIAG_EN = 5 V, when IOUT < I(ol,on), duration longer than td(ol,on), open load is detected. | 200 | 300 | 450 | µs |
I(ol,on) | Open-load detection threshold in on-state | VIN = 5 V, VDIAG_EN = 5 V, when IOUT < I(ol,on), duration longer than td(ol,on), open load is detected. | 1 | 5 | 8 | mA |
V(ol,off) | Open-load detection threshold in off-state | VIN = 0 V, VDIAG_EN = 5 V, when VVS – VOUT < V(ol,off), duration longer than td(ol,off), open load is detected. | 1.4 | 2.6 | V | |
td(ol,off) | Open-load deglitch time in off-state | VIN = 0 V, VDIAG_EN = 5 V, when VVS – VOUT < V(ol,off), duration longer than td(ol,off), open load is detected. | 200 | 300 | 450 | µs |
I(ol,off) | Off-state output sink current | VIN = 0 V, VDIAG_EN = 5 V, VVS = VOUT = 13.5 V | –70 | µA | ||
VFAULT | FAULT low output voltage | IFAULT = 2 mA | 0.2 | V | ||
tFAULT | FAULT signal holding time(1) | 8.5 | ms | |||
T(SD) | Thermal shutdown threshold(1) | 175 | °C | |||
T(SD,rst) | Thermal shutdown status reset(1) | 155 | °C | |||
T(sw) | Thermal swing shutdown threshold(1) | 60 | °C | |||
T(hys) | Hysterisis for resetting the thermal shutdown and swing(1) | 10 | °C | |||
CURRENT LIMIT AND DELAY CONFIGURATION | ||||||
K(CL) | Current-limit current ratio(1) | 600 | ||||
VCL(th) | Current-limit internal threshold voltage(1) | 0.8 | V | |||
dK(CL)/K(CL) | External current limit accuracy(2) (IOUT – ICL × K(CL)) × 100 / (ICL × K(CL)) | Ilimit ≥ 0.05 A, VVS – VOUT ≥ 2.5V | –20% | 20% | ||
Ilimit ≥ 0.15 A , VVS – VOUT ≥ 2.5V | –15% | 15% | ||||
Ilimit ≥ 0.3 A, Ilimit < 1 A, VVS – VOUT ≥ 2.5V | –10% | 10% | ||||
Idl(chg) | Delay pin charging current in latch-off mode(1) | 4.5 | µA | |||
Vdl(th) | Pulling up threshold in auto-retry mode | 2.7 | V | |||
Vdl(ref) | Internal reference voltage in latch-off mode | 1.45 | V | |||
tdl1 | Internal fixed delay time(1) | 300 | 400 | 500 | µs | |
tdl2 | Adjustable delay time by external capacitor on DELAY pin(1) | Connect with 3.3 uF capacitor as the maximum value. | 1000 | ms | ||
tCL(deg) | Deglitch time when current limit (1) | IN low to high, VDIAG_EN = 5 V, the deglitch time from IN rising edge to FAULT reporting out. | 300 | 500 | µs | |
IN keeps high, VDIAG_EN = 5 V, the deglitch time from CL start-point to FAULT reporting out. | 80 | 180 | ||||
thic(on) | On-time when in auto-retry mode(1) | 35 | 40 | 45 | ms | |
thic(off) | Off-time when in auto-retry mode(1) | 0.8 | 1 | 1.2 | s |