SLVSDR1A February 2018 – April 2020 ADC08DJ3200
PRODUCTION DATA.
The ADC08DJ3200 can be programmed as a single-channel or dual-channel ADC and a number JESD204B output formats. Table 8 summarizes the basic operating mode configuration parameters and whether they are user configured or derived.
NOTE
Powering down high-speed data outputs (DA0± ... DA7±, DB0± ... DB7±) for extended times can reduce performance of the output serializers, especially at high data rates. For information regarding reliable serializer operation, see the Power-Down Modes section.
PARAMETER | DESCRIPTION | USER CONFIGURED OR DERIVED | VALUE |
---|---|---|---|
JMODE | JESD204B operating mode, automatically derives the rest of the JESD204B parameters, single-channel or dual-channel mode | User configured | Set by JMODE (see the JESD204B mode register) |
D | Decimation factor | Derived | See Table 10 |
DES | 1 = single-channel mode, 0 = dual-channel mode | Derived | See Table 10 |
R | Number of bits transmitted per lane per DEVCLK cycle. The JESD204B line rate is the DEVCLK frequency times R. This parameter sets the SerDes PLL multiplication factor or controls bypassing of the SerDes PLL. | Derived | See Table 10 |
Links | Number of JESD204B links used | Derived | See Table 10 |
K | Number of frames per multiframe | User configured | Set by KM1 (see the JESD204B K parameter register), see the allowed values in Table 10 |
There are a number of parameters required to define the JESD204B format, all of which are sent across the link during the initial lane alignment sequence. In the ADC08DJ3200, most parameters are automatically derived based on the selected JMODE; however, a few are configured by the user. Table 9 describes these parameters.
PARAMETER | DESCRIPTION | USER CONFIGURED OR DERIVED | VALUE |
---|---|---|---|
ADJCNT | LMFC adjustment amount (not applicable) | Derived | Always 0 |
ADJDIR | LMFC adjustment direction (not applicable) | Derived | Always 0 |
BID | Bank ID | Derived | Always 0 |
CF | Number of control words per frame | Derived | Always 0 |
CS | Control bits per sample | Derived | Always set to 0 in ILAS, see Table 10 for actual usage |
DID | Device identifier, used to identify the link | User configured | Set by DID (see the JESD204B DID parameter register), see Table 11 |
F | Number of octets (bytes) per frame (per lane) | Derived | See Table 10 |
HD | High-density format (samples split between lanes) | Derived | Always 0 |
JESDV | JESD204 standard revision | Derived | Always 1 |
K | Number of frames per multiframe | User configured | Set by the KM1 register, see the JESD204B K parameter register |
L | Number of serial output lanes per link | Derived | See Table 10 |
LID | Lane identifier for each lane | Derived | See Table 11 |
M | Number of converters used to determine lane bit packing; may not match number of ADC channels in the device | Derived | See Table 10 |
N | Sample resolution (before adding control and tail bits) | Derived | See Table 10 |
N' | Bits per sample after adding control and tail bits | Derived | See Table 10 |
S | Number of samples per converter (M) per frame | Derived | See Table 10 |
SCR | Scrambler enabled | User configured | Set by the JESD204B control register |
SUBCLASSV | Device subclass version | Derived | Always 1 |
RES1 | Reserved field 1 | Derived | Always 0 |
RES2 | Reserved field 2 | Derived | Always 0 |
CHKSUM | Checksum for ILAS checking (sum of all above parameters modulo 256) | Derived | Computed based on parameters in this table |
Configuring the ADC08DJ3200 is made easy by using a single configuration parameter called JMODE (see the JESD204B mode register). Using Table 10, the correct JMODE value can be found for the desired operating mode. The modes listed in Table 10 are the only available operating modes. This table also gives a range and allowable step size for the K parameter (set by KM1, see the JESD204B K parameter register), which sets the multiframe length in number of frames.
ADC08DJ3200 OPERATING MODE | USER-SPECIFIED PARAMETER | DERIVED PARAMETERS | INPUT CLOCK RANGE (MHz) | |||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
JMODE | K
[Min:Step:Max] |
D | DES | LINKS | N | CS | N’ | L
(Per Link) |
M
(Per Link) |
F | S | R
(Fbit / Fclk) |
||
Reserved | 0-3 | — | — | — | — | — | — | — | — | — | — | — | — | — |
8-bit, single-channel, 4 lanes | 4 | 18:2:32 | 1 | 1 | 2 | 8 | 0 | 8 | 2 | 1 | 1 | 2 | 5 | 800-2560 |
8-bit, single-channel, 8 lanes | 5 | 18:2:32 | 1 | 1 | 2 | 8 | 0 | 8 | 4 | 1 | 1 | 4 | 2.5 | 800-3200 |
8-bit, dual-channel, 4 lanes | 6 | 18:2:32 | 1 | 0 | 2 | 8 | 0 | 8 | 2 | 1 | 1 | 2 | 5 | 800-2560 |
8-bit, dual-channel, 8 lanes | 7 | 18:2:32 | 1 | 0 | 2 | 8 | 0 | 8 | 4 | 1 | 1 | 4 | 2.5 | 800-3200 |
Reserved | 8-16 | — | — | — | — | — | — | — | — | — | — | — | — | — |
8-bit, single-channel, 16 lanes | 17 | 18:2:32 | 1 | 1 | 2 | 8 | 0 | 8 | 8 | 1 | 1 | 8 | 1.25 | 800-3200 |
8-bit, dual-channel, 16 lanes | 18 | 18:2:32 | 1 | 0 | 2 | 8 | 0 | 8 | 8 | 1 | 1 | 8 | 1.25 | 800-3200 |
The ADC08DJ3200 has a total of 16 high-speed output drivers that are grouped into two 8-lane JESD204B links. Most operating modes use two links with up to eight lanes per link. The lanes and their derived configuration parameters are described in Table 11. For a specified JMODE, the lowest indexed lanes for each link are used and the higher indexed lanes for each link are automatically powered down. Always route the lowest indexed lanes to the logic device.
DEVICE PIN DESIGNATION | LINK | DID (User Configured) | LID (Derived) |
---|---|---|---|
DA0± | A | Set by DID (see the JESD204B DID parameter register), the effective DID is equal to the DID register setting (DID) | 0 |
DA1± | 1 | ||
DA2± | 2 | ||
DA3± | 3 | ||
DA4± | 4 | ||
DA5± | 5 | ||
DA6± | 6 | ||
DA7± | 7 | ||
DB0± | B | Set by DID (see the JESD204B DID parameter register), the effective DID is equal to the DID register setting plus 1 (DID+1) | 0 |
DB1± | 1 | ||
DB2± | 2 | ||
DB3± | 3 | ||
DB4± | 4 | ||
DB5± | 5 | ||
DB6± | 6 | ||
DB7± | 7 |