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ADC12DJ3200QML-SP 6.4GSPS, Single-Channel or 3.2GSPS, Dual-Channel, 12-Bit, RF-Sampling Analog-to-Digital Converter (ADC)
SLVSDR2C
November 2018 – March 2025
ADC12DJ3200QML-SP
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ADC12DJ3200QML-SP 6.4GSPS, Single-Channel or 3.2GSPS, Dual-Channel, 12-Bit, RF-Sampling Analog-to-Digital Converter (ADC)
1
1
Features
2
Applications
3
Description
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics: DC Specifications
5.6
Electrical Characteristics: Power Consumption
5.7
Electrical Characteristics: AC Specifications (Dual-Channel Mode)
5.8
Electrical Characteristics: AC Specifications (Single-Channel Mode)
5.9
Timing Requirements
5.10
Switching Characteristics
5.11
Timing Diagrams
5.12
Typical Characteristics
6
Detailed Description
6.1
Overview
6.2
Functional Block Diagram
6.3
Feature Description
6.3.1
Analog Inputs
6.3.1.1
Analog Input Protection
6.3.1.2
Full-Scale Voltage (VFS) Adjustment
6.3.1.3
Analog Input Offset Adjust
6.3.2
ADC Core
6.3.2.1
ADC Theory of Operation
6.3.2.2
ADC Core Calibration
6.3.2.3
ADC Overrange Detection
6.3.2.4
Code Error Rate (CER)
6.3.3
Timestamp
6.3.4
Clocking
6.3.4.1
Noiseless Aperture Delay Adjustment (tAD Adjust)
6.3.4.2
Aperture Delay Ramp Control (TAD_RAMP)
6.3.4.3
SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
6.3.4.3.1
SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
6.3.4.3.2
Automatic SYSREF Calibration
6.3.5
Digital Down Converters (Dual-Channel Mode Only)
6.3.5.1
Numerically-Controlled Oscillator and Complex Mixer
6.3.5.1.1
NCO Fast Frequency Hopping (FFH)
6.3.5.1.2
NCO Selection
6.3.5.1.3
Basic NCO Frequency Setting Mode
6.3.5.1.4
Rational NCO Frequency Setting Mode
6.3.5.1.5
NCO Phase Offset Setting
6.3.5.1.6
NCO Phase Synchronization
6.3.5.2
Decimation Filters
6.3.5.3
Output Data Format
6.3.5.4
Decimation Settings
6.3.5.4.1
Decimation Factor
6.3.5.4.2
DDC Gain Boost
6.3.6
JESD204B Interface
6.3.6.1
Transport Layer
6.3.6.2
Scrambler
6.3.6.3
Link Layer
6.3.6.3.1
Code Group Synchronization (CGS)
6.3.6.3.2
Initial Lane Alignment Sequence (ILAS)
6.3.6.3.3
8b, 10b Encoding
6.3.6.3.4
Frame and Multiframe Monitoring
6.3.6.4
Physical Layer
6.3.6.4.1
SerDes Pre-Emphasis
6.3.6.5
JESD204B Enable
6.3.6.6
Multi-Device Synchronization and Deterministic Latency
6.3.6.7
Operation in Subclass 0 Systems
6.3.7
Alarm Monitoring
6.3.7.1
NCO Upset Detection
6.3.7.2
Clock Upset Detection
6.3.8
Temperature Monitoring Diode
6.3.9
Analog Reference Voltage
6.4
Device Functional Modes
6.4.1
Dual-Channel Mode
6.4.2
Single-Channel Mode (DES Mode)
6.4.3
JESD204B Modes
6.4.3.1
JESD204B Output Data Formats
6.4.3.2
Dual DDC and Redundant Data Mode
6.4.4
Power-Down Modes
6.4.5
Test Modes
6.4.5.1
Serializer Test-Mode Details
6.4.5.2
PRBS Test Modes
6.4.5.3
Ramp Test Mode
6.4.5.4
Short and Long Transport Test Mode
6.4.5.4.1
Short Transport Test Pattern
6.4.5.4.2
Long Transport Test Pattern
6.4.5.5
D21.5 Test Mode
6.4.5.6
K28.5 Test Mode
6.4.5.7
Repeated ILA Test Mode
6.4.5.8
Modified RPAT Test Mode
6.4.6
Calibration Modes and Trimming
6.4.6.1
Foreground Calibration Mode
6.4.6.2
Background Calibration Mode
6.4.6.3
Low-Power Background Calibration (LPBG) Mode
6.4.7
Offset Calibration
6.4.8
Trimming
6.4.9
Offset Filtering
6.5
Programming
6.5.1
Using the Serial Interface
6.5.1.1
SCS
6.5.1.2
SCLK
6.5.1.3
SDI
6.5.1.4
SDO
6.5.1.5
Streaming Mode
6.6
Register Maps
6.6.1
Register Descriptions
6.6.2
SYSREF Calibration Registers (0x2B0 to 0x2BF)
6.6.3
Alarm Registers (0x2C0 to 0x2C2)
7
Application Information Disclaimer
7.1
Application Information
7.1.1
Analog Inputs
7.1.2
Analog Input Bandwidth
7.1.3
Clocking
7.1.4
Radiation Environment Recommendations
7.1.4.1
Single Event Latch-Up (SEL)
7.1.4.2
Single Event Functional Interrupt (SEFI)
7.1.4.3
Single Event Upset (SEU)
7.2
Typical Application
7.2.1
Design Requirements
7.2.2
Detailed Design Procedure
7.2.2.1
RF Input Signal Path
7.2.2.2
Calculating Values of AC-Coupling Capacitors
7.2.3
Application Curves
7.3
Initialization Set Up
Power Supply Recommendations
7.4.1
Power Sequencing
7.4
Layout
7.4.1
Layout Guidelines
7.4.2
Layout Example
8
Device and Documentation Support
8.1
Device Support
8.1.1
Development Support
8.2
Documentation Support
8.2.1
Related Documentation
8.3
Third-Party Products Disclaimer
8.4
Receiving Notification of Documentation Updates
8.5
Support Resources
8.6
Trademarks
8.7
Electrostatic Discharge Caution
8.8
Glossary
9
Revision History
10
Mechanical, Packaging, and Orderable Information
IMPORTANT NOTICE
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Data Sheet
ADC12DJ3200QML-SP 6.4GSPS, Single-Channel or 3.2GSPS, Dual-Channel, 12-Bit, RF-Sampling Analog-to-Digital Converter (ADC)
1
Features
ADC core:
12-Bit resolution
Up to 6.4GSPS in single-channel mode
Up to 3.2GSPS in dual-channel mode
Noise floor (no signal, V
FS
= 1V
PP-DIFF
):
Dual-channel mode: –149.5dBFS/Hz
Single-channel mode: –152.4dBFS/Hz
Peak noise power ratio (NPR): 45.4dB
Buffered analog inputs with V
CMI
of 0V:
Analog input bandwidth (–3dB): 7GHz
Usable input frequency range: >10GHz
Full-scale input voltage (V
FS
, default): 0.8V
PP
Noiseless aperture delay (t
AD
) adjustment:
Precise sampling control: 19fs step size
Temperature and voltage invariant delays
Easy-to-use synchronization features
Automatic SYSREF timing calibration
Timestamp for sample marking
JESD204B subclass-1 compliant interface:
Maximum lane rate: 12.8Gbps
Up to 16 lanes allows reduced lane rate
Digital down-converters in dual-channel mode:
Real output: DDC bypass or 2x decimation
Complex output: 4x, 8x, or 16x decimation
Radiation performance:
Total Ionizing Dose (TID): 300krad (Si)
Single Event Latchup (SEL): 120MeV-cm
2
/mg
Single Event Upset (SEU) immune registers
Power consumption: 3W
2
Applications
Satellite communications (SATCOM)
Phased array radar, SIGINT, and ELINT
Synthetic aperture radar (SAR)
Time-of-flight
and LIDAR distance measurement
RF Sampling software-defined radio (SDR)
Spectrometry
