SLVSDR2 Data sheet

SLVSDR2B November 2018 – March 2021 ADC12DJ3200QML-SP

PRODUCTION DATA

6.10 Switching Characteristics

typical values at T_A = 25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000), input signal applied to INA± in single-channel modes, f_IN = 347 MHz, A_IN = –1dBFS, f_CLK = maximum-rated clock frequency, filtered 1-V_PP sine-wave clock, JMODE = 1, and background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over the operating temperature range provided in the Recommended Operating Conditions table

PARAMETER		TEST CONDITIONS	SUBGROUP⁽¹⁾	MIN	TYP	MAX	UNIT
DEVICE (SAMPLING) CLOCK (CLK+, CLK–)
t_AD	Sampling (aperture) delay from CLK± rising edge (dual-channel mode) or rising and falling edge (single-channel mode) to sampling instant	TAD_COARSE = 0x00, TAD_FINE = 0x00 and TAD_INV = 0			350		ps
t_AD(MAX)	Maximum t_AD Adjust programmable delay, not including clock inversion (TAD_INV = 0)	Coarse adjustment (TAD_COARSE = 0xFF)			289		ps
t_AD(MAX)		Fine adjustment (TAD_FINE = 0xFF)			4.9		ps
t_AD(STEP)	t_AD Adjust programmable delay step size	Coarse adjustment (TAD_COARSE)			1.13		ps
t_AD(STEP)	t_AD Adjust programmable delay step size	Fine adjustment (TAD_FINE)			19		ps
t_AJ	Aperture jitter, rms	Minimum t_AD adjust coarse setting (TAD_COARSE = 0x00, TAD_INV = 0)			56		fs
t_AJ	Aperture jitter, rms	Maximum t_AD adjust coarse setting (TAD_COARSE = 0xFF) excluding TAD_INV (TAD_INV = 0)			68⁽⁴⁾		fs
SERIAL DATA OUTPUTS (DA[7:0]+, DA[7:0]–, DB[7:0]+, DB[7:0]–)
f_SERDES	Serialized output bit rate	Maximum output bit rate	[9, 10, 11]	12.8			Gbps
f_SERDES	Serialized output bit rate	Minimum output bit rate			1		Gbps
UI	Serialized output unit interval	Minimum output unit interval	[9, 10, 11]			78.125	ps
UI	Serialized output unit interval	Maximum output unit interval			1000		ps
t_TLH	Low-to-high transition time (differential)	20% to 80%, PRBS-7 test pattern, 12.8 Gbps, SER_PE = 0x04			27		ps
t_THL	High-to-low transition time (differential)	20% to 80%, PRBS-7 test pattern, 12.8 Gbps, SER_PE = 0x04			27		ps
DDJ	Data dependent jitter, peak-to-peak	PRBS-7 test pattern, 12.8 Gbps, SER_PE = 0x04, JMODE = 2			11.7		ps
RJ	Random jitter, RMS	PRBS-7 test pattern, 12.8 Gbps, SER_PE = 0x04, JMODE = 2			0.8		ps
TJ	Total jitter, peak-to-peak, with gaussian portion defined with respect to a BER=1e-15 (Q = 7.94)	PRBS-7 test pattern, 12.8 Gbps, SER_PE = 0x04, JMODE = 0, 2			24		ps
		PRBS-7 test pattern, 6.4 Gbps, SER_PE = 0x04, JMODE = 1, 3			20
		PRBS-7 test pattern, 8 Gbps, SER_PE = 0x04, JMODE = 4, 5, 6, 7			31
		PRBS-7 test pattern, 8 Gbps, SER_PE = 0x04, JMODE = 9			32
		PRBS-7 test pattern, 8 Gbps, SER_PE = 0x04, JMODE = 10, 11			35
		PRBS-7 test pattern, 3.2 Gbps, SER_PE = 0x04, JMODE = 12			24
		PRBS-7 test pattern, 8 Gbps, SER_PE = 0x04, JMODE = 13, 14			35
		PRBS-7 test pattern, 8 Gbps, SER_PE = 0x04, JMODE = 15, 16			31
ADC CORE LATENCY
t_ADC	Deterministic delay from the CLK± edge that samples the reference sample to the CLK± edge that samples SYSREF going high⁽²⁾	JMODE = 0			–8.5		t_CLK cycles
		JMODE = 1			–20.5
		JMODE = 2			–9
		JMODE = 3			–21
		JMODE = 4			–4.5
		JMODE = 5			–24.5
		JMODE = 6			–5
		JMODE = 7			–25
		JMODE = 9			60
		JMODE = 10			140
		JMODE = 11			136
		JMODE = 12			120
		JMODE = 13			232
		JMODE = 14			232
		JMODE = 15			446
		JMODE = 16			430
		JMODE = 17			–48.5
		JMODE = 18			–49
JESD204B AND SERIALIZER LATENCY
t_TX	Delay from the CLK± rising edge that samples SYSREF high to the first bit of the multiframe on the JESD204B serial output lane corresponding to the reference sample of t_ADC⁽³⁾	JMODE = 0		72⁽⁵⁾		84⁽⁵⁾	t_CLK cycles
		JMODE = 1		119⁽⁵⁾		132⁽⁵⁾
		JMODE = 2		72⁽⁵⁾		84⁽⁵⁾
		JMODE = 3		119⁽⁵⁾		132⁽⁵⁾
		JMODE = 4		67⁽⁵⁾		80⁽⁵⁾
		JMODE = 5		106⁽⁵⁾		119⁽⁵⁾
		JMODE = 6		67⁽⁵⁾		80⁽⁵⁾
		JMODE = 7		106⁽⁵⁾		119⁽⁵⁾
		JMODE = 9		106⁽⁵⁾		119⁽⁵⁾
		JMODE = 10		67⁽⁵⁾		80⁽⁵⁾
		JMODE = 11		106⁽⁵⁾		119⁽⁵⁾
		JMODE = 12		213⁽⁵⁾		225⁽⁵⁾
		JMODE = 13		67⁽⁵⁾		80⁽⁵⁾
		JMODE = 14		106⁽⁵⁾		119⁽⁵⁾
		JMODE = 15		67⁽⁵⁾		80⁽⁵⁾
		JMODE = 16		106⁽⁵⁾		119⁽⁵⁾
		JMODE = 17		195⁽⁵⁾		208⁽⁵⁾
		JMODE = 18		195⁽⁵⁾		208⁽⁵⁾
SERIAL PROGRAMMING INTERFACE (SDO)
t_(OZD)	Delay from falling edge of 16th SCLK cycle during read operation for SDO transition from tri-state to valid data			1⁽⁵⁾			ns
t_(ODZ)	Delay from SCS rising edge for SDO transition from valid data to tri-state					10⁽⁵⁾	ns
t_(OD)	Delay from falling edge of SCLK during read operation to SDO valid		[4, 5, 6]	1		10	ns

(1) For subgroup definitions, please see Table 6-1.

(2) t_ADC is an exact, unrounded, deterministic delay. The delay can be negative if the reference sample is sampled after the SYSREF high capture point, in which case the total latency is smaller than the delay given by t_TX.

(3) The values given for t_TX include deterministic and non-deterministic delays. The delay varies over process, temperature, and voltage. JESD204B accounts for these variations when operating in subclass-1 mode in order to achieve deterministic latency. Proper receiver RBD values must be chosen such that the elastic buffer release point does not occur within the invalid region of the local multiframe clock (LMFC) cycle.

(4) t_AJ increases because of additional attenuation on the internal clock path.

(5) This parameter is specified by design and is not tested in production.