SLVSDR2B November   2018  – March 2021 ADC12DJ3200QML-SP

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: DC Specifications
    6. 6.6  Electrical Characteristics: Power Consumption
    7. 6.7  Electrical Characteristics: AC Specifications (Dual-Channel Mode)
    8. 6.8  Electrical Characteristics: AC Specifications (Single-Channel Mode)
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Timing Diagrams
    12. 6.12 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
        1. 7.3.1.1 Analog Input Protection
        2. 7.3.1.2 Full-Scale Voltage (VFS) Adjustment
        3. 7.3.1.3 Analog Input Offset Adjust
      2. 7.3.2 ADC Core
        1. 7.3.2.1 ADC Theory of Operation
        2. 7.3.2.2 ADC Core Calibration
        3. 7.3.2.3 ADC Overrange Detection
        4. 7.3.2.4 Code Error Rate (CER)
      3. 7.3.3 Timestamp
      4. 7.3.4 Clocking
        1. 7.3.4.1 Noiseless Aperture Delay Adjustment (tAD Adjust)
        2. 7.3.4.2 Aperture Delay Ramp Control (TAD_RAMP)
        3. 7.3.4.3 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          1. 7.3.4.3.1 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
          2. 7.3.4.3.2 Automatic SYSREF Calibration
      5. 7.3.5 Digital Down Converters (Dual-Channel Mode Only)
        1. 7.3.5.1 Numerically-Controlled Oscillator and Complex Mixer
          1. 7.3.5.1.1 NCO Fast Frequency Hopping (FFH)
          2. 7.3.5.1.2 NCO Selection
          3. 7.3.5.1.3 Basic NCO Frequency Setting Mode
          4. 7.3.5.1.4 Rational NCO Frequency Setting Mode
          5. 7.3.5.1.5 NCO Phase Offset Setting
          6. 7.3.5.1.6 NCO Phase Synchronization
        2. 7.3.5.2 Decimation Filters
        3. 7.3.5.3 Output Data Format
        4. 7.3.5.4 Decimation Settings
          1. 7.3.5.4.1 Decimation Factor
          2. 7.3.5.4.2 DDC Gain Boost
      6. 7.3.6 JESD204B Interface
        1. 7.3.6.1 Transport Layer
        2. 7.3.6.2 Scrambler
        3. 7.3.6.3 Link Layer
          1. 7.3.6.3.1 Code Group Synchronization (CGS)
          2. 7.3.6.3.2 Initial Lane Alignment Sequence (ILAS)
          3. 7.3.6.3.3 8b, 10b Encoding
          4. 7.3.6.3.4 Frame and Multiframe Monitoring
        4. 7.3.6.4 Physical Layer
          1. 7.3.6.4.1 SerDes Pre-Emphasis
        5. 7.3.6.5 JESD204B Enable
        6. 7.3.6.6 Multi-Device Synchronization and Deterministic Latency
        7. 7.3.6.7 Operation in Subclass 0 Systems
      7. 7.3.7 Alarm Monitoring
        1. 7.3.7.1 NCO Upset Detection
        2. 7.3.7.2 Clock Upset Detection
      8. 7.3.8 Temperature Monitoring Diode
      9. 7.3.9 Analog Reference Voltage
    4. 7.4 Device Functional Modes
      1. 7.4.1 Dual-Channel Mode
      2. 7.4.2 Single-Channel Mode (DES Mode)
      3. 7.4.3 JESD204B Modes
        1. 7.4.3.1 JESD204B Output Data Formats
        2. 7.4.3.2 Dual DDC and Redundant Data Mode
      4. 7.4.4 Power-Down Modes
      5. 7.4.5 Test Modes
        1. 7.4.5.1 Serializer Test-Mode Details
        2. 7.4.5.2 PRBS Test Modes
        3. 7.4.5.3 Ramp Test Mode
        4. 7.4.5.4 Short and Long Transport Test Mode
          1. 7.4.5.4.1 Short Transport Test Pattern
          2. 7.4.5.4.2 Long Transport Test Pattern
        5. 7.4.5.5 D21.5 Test Mode
        6. 7.4.5.6 K28.5 Test Mode
        7. 7.4.5.7 Repeated ILA Test Mode
        8. 7.4.5.8 Modified RPAT Test Mode
      6. 7.4.6 Calibration Modes and Trimming
        1. 7.4.6.1 Foreground Calibration Mode
        2. 7.4.6.2 Background Calibration Mode
        3. 7.4.6.3 Low-Power Background Calibration (LPBG) Mode
      7. 7.4.7 Offset Calibration
      8. 7.4.8 Trimming
      9. 7.4.9 Offset Filtering
    5. 7.5 Programming
      1. 7.5.1 Using the Serial Interface
        1. 7.5.1.1 SCS
        2. 7.5.1.2 SCLK
        3. 7.5.1.3 SDI
        4. 7.5.1.4 SDO
        5. 7.5.1.5 Streaming Mode
    6. 7.6 Register Maps
      1. 7.6.1 Register Descriptions
      2. 7.6.2 SYSREF Calibration Registers (0x2B0 to 0x2BF)
      3. 7.6.3 Alarm Registers (0x2C0 to 0x2C2)
  8. 8 Application Information Disclaimer
    1. 8.1 Application Information
      1. 8.1.1 Analog Inputs
      2. 8.1.2 Analog Input Bandwidth
      3. 8.1.3 Clocking
      4. 8.1.4 Radiation Environment Recommendations
        1. 8.1.4.1 Single Event Latch-Up (SEL)
        2. 8.1.4.2 Single Event Functional Interrupt (SEFI)
        3. 8.1.4.3 Single Event Upset (SEU)
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 RF Input Signal Path
        2. 8.2.2.2 Calculating Values of AC-Coupling Capacitors
      3. 8.2.3 Application Curves
    3. 8.3 Initialization Set Up
  9. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Community Resources
    5. 10.5 Trademarks

5 Pin Configuration and Functions

GUID-F5BC29F4-9EBE-4C8C-8B8A-A77143F99133-low.gifFigure 5-1 ZMX (CGLA) and NWE (CCGA)Package,196-Pad Flip Chip Ceramic LGA,Top View
Table 5-1 Pin Functions
PIN I/O DESCRIPTION
NAME NO.
AGND A1, A3, A6, B1, B3, B4, B6, B6, C6, C7, D4, D5, D6, D7, E4, E5, E6, E7, F1, F4, F5, F6, F7, G2, G4, G5, G6, G7, H2, H4, H5, H6, H7, J1, J4, J5, J6, J7, K4, K5, K6, K7, L4, L5, L6, L7, M6, M7, N1, N3, N4, N5, N6, P1, P3, P6 — Analog supply ground. AGND and DGND should be directly connected on circuit board.
BG A2 O Bandgap voltage output. This pin is capable of sourcing 100 μA and can drive a load up to 80 pF. See the Analog Reference Voltage section for more details. This pin can be left disconnected if not used.
CALSTAT B9 O Foreground calibration status output or device alarm output. Functionality is programmed through CAL_STATUS_SEL. This pin can be left disconnected if not used.
CALTRIG A9 I Foreground calibration trigger input. This pin is only used if hardware calibration triggering is selected in CAL_TRIG_EN, otherwise software triggering is performed using CAL_SOFT_TRIG. This pin should be tied to GND if not used.
CLK+ G1 I Device (sampling) clock positive input. The clock signal must be AC coupled to this input. In single-channel mode, the analog input signal is sampled on both rising and falling edges. In dual-channel mode, the analog signal is sampled on the rising edge. This differential input has an internal 100-Ω differential termination and is self-biased to the optimal input common mode voltage.
CLK– H1 I Device (sampling) clock negative input. Must be AC coupled.
DA0+ E14 O High-speed serialized-data output for channel A, lane 0, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DA0– F14 O High-speed serialized-data output for channel A, lane 0, negative connection. This pin can be left disconnected if not used.
DA1+ C14 O High-speed serialized-data output for channel A, lane 1, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DA1– D14 O High-speed serialized-data output for channel A, lane 1, negative connection. This pin can be left disconnected if not used.
DA2+ A12 O High-speed serialized-data output for channel A, lane 2, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DA2– A13 O High-speed serialized-data output for channel A, lane 2, negative connection. This pin can be left disconnected if not used.
DA3+ A10 O High-speed serialized-data output for channel A, lane 3, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DA3– A11 O High-speed serialized-data output for channel A, lane 3, negative connection. This pin can be left disconnected if not used.
DA4+ E13 O High-speed serialized-data output for channel A, lane 4, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DA4– F13 O High-speed serialized-data output for channel A, lane 4, negative connection. This pin can be left disconnected if not used.
DA5+ C13 O High-speed serialized-data output for channel A, lane 5, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DA5– D13 O High-speed serialized-data output for channel A, lane 5, negative connection. This pin can be left disconnected if not used.
DA6+ B12 O High-speed serialized-data output for channel A, lane 6, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DA6– B13 O High-speed serialized-data output for channel A, lane 6, negative connection. This pin can be left disconnected if not used.
DA7+ B10 O High-speed serialized-data output for channel A, lane 7, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DA7– B11 O High-speed serialized-data output for channel A, lane 7, negative connection. This pin can be left disconnected if not used.
DB0+ K14 O High-speed serialized-data output for channel B, lane 0, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DB0– J14 O High-speed serialized-data output for channel B, lane 0, negative connection. This pin can be left disconnected if not used.
DB1+ M14 O High-speed serialized-data output for channel B, lane 1, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DB1– L14 O High-speed serialized-data output for channel B, lane 1, negative connection. This pin can be left disconnected if not used.
DB2+ P12 O High-speed serialized-data output for channel B, lane 2, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DB2– P13 O High-speed serialized-data output for channel B, lane 2, negative connection. This pin can be left disconnected if not used.
DB3+ P10 O High-speed serialized-data output for channel B, lane 3, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DB3– P11 O High-speed serialized-data output for channel B, lane 3, negative connection. This pin can be left disconnected if not used.
DB4+ K13 O High-speed serialized-data output for channel B, lane 4, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DB4– J13 O High-speed serialized-data output for channel B, lane 4, negative connection. This pin can be left disconnected if not used.
DB5+ M13 O High-speed serialized-data output for channel B, lane 5, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DB5– L13 O High-speed serialized-data output for channel B, lane 5, negative connection. This pin can be left disconnected if not used.
DB6+ N12 O High-speed serialized-data output for channel B, lane 6, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DB6– N13 O High-speed serialized-data output for channel B, lane 6, negative connection. This pin can be left disconnected if not used.
DB7+ N10 O High-speed serialized-data output for channel B, lane 7, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DB7– N11 O High-speed serialized-data output for channel B, lane 7, negative connection. This pin can be left disconnected if not used.
DGND A14, B14, C8, C9, D8, D9, D10, D11, E8, E9, E10, E11, F8, F9, F10, F11, G8, G9, G10, G11, H8, H9, H10, H11, J8, J9, J10, J11, K8, K9, K10, K11, L8, L9, L10, L11, M8, M9, N9, N14, P14 — Digital supply ground. AGND and DGND should be directly connected on circuit board.
INA+ A4 I Channel A analog input positive connection. The differential full-scale input range is determined by the full-scale voltage adjust register. The input common mode voltage should be set to AGND. This input is terminated to ground through a 50-Ω termination resistor. Use of INA is recommended for single-channel mode due to optimized performance. This pin can be left disconnected if not used.
INA– A5 I Channel A analog input negative connection. This input is terminated to ground through a 50-Ω termination resistor. Use of INA is recommended for single-channel mode due to optimized performance. This pin can be left disconnected if not used.
INB+ P4 I Channel B analog input positive connection. The differential full-scale input range is determined by the full-scale voltage adjust register. The input common mode voltage should be set to AGND. This input is terminated to ground through a 50-Ω termination resistor. This pin can be left disconnected if not used.
INB– P5 I Channel B analog input negative connection. This input is terminated to ground through a 50-Ω termination resistor. This pin can be left disconnected if not used.
NCOA0 A7 I NCO accumulator selection control LSB for DDC A. NCOA0 and NCOA1 select which NCO, of a possible four NCOs, is used for digital mixing. The remaining unselected NCOs continue to run to maintain phase coherency and can be swapped in by changing the values of NCOA0 and NCOA1. This is an asynchronous input. This pin should be tied to GND if not used.
NCOA1 B7 I NCO accumulator selection control MSB for DDC A. This pin should be tied to GND if not used.
NCOB0 P7 I NCO accumulator selection control LSB for DDC B. NCOB0 and NCOB1 select which NCO, of a possible four NCOs, is used for digital mixing. The remaining unselected NCOs continue to run to maintain phase coherency and can be swapped in by changing the values of NCOB0 and NCOB1. This is an asynchronous input. This pin should be tied to GND if not used.
NCOB1 N7 I NCO accumulator selection control MSB for DDC B. This pin should be tied to GND if not used.
ORA0 A8 O Fast overrange detection status for channel A for T0 threshold. When the analog input exceeds the threshold programmed into OVR_T0, this status will go high. The minimum pulse duration is set by OVR_N. This pin can be left disconnected if not used.
ORA1 B8 O Fast overrange detection status for channel A for T1 threshold. When the analog input exceeds the threshold programmed into OVR_T1, this status will go high. The minimum pulse duration is set by OVR_N. This pin can be left disconnected if not used.
ORB0 P8 O Fast overrange detection status for channel B for T0 threshold. When the analog input exceeds the threshold programmed into OVR_T0, this status will go high. The minimum pulse duration is set by OVR_N. This pin can be left disconnected if not used.
ORB1 N8 O Fast overrange detection status for channel B for T1 threshold. When the analog input exceeds the threshold programmed into OVR_T1, this status will go high. The minimum pulse duration is set by OVR_N. This pin can be left disconnected if not used.
PD P9 I This pin disables all analog circuits and serializer outputs when set high for temperature diode calibration only. Do not use this pin to power down the device for power savings. Tie this pin to GND during normal operation. For information regarding reliable serializer operation, see the Power down Modes section.
SCLK G14 I Serial interface clock. This pin functions as the serial-interface clock input which clocks the serial programming data in and out. Using the Serial Inrterface describes the serial interface in more detail. This pin supports 1.1 V to 1.9 V CMOS levels.
SCS G13 I Serial interface chip select active low input. Using the Serial Inrterface describes the serial interface in more detail. This pin supports 1.1 V to 1.9 V CMOS levels. This pin has a 82-kΩ pull-up resistor to VD11.
SDI H13 I Serial interface data input. Using the Serial Inrterface describes the serial interface in more detail. This pin supports 1.1 V to 1.9 V CMOS levels.
SDO H14 O Serial interface data output. Using the Serial Inrterface describes the serial interface in more detail. This pin is high impedance during normal device operation. This pin outputs 1.9-V CMOS levels during serial interface read operations. This pin can be left disconnected if not used.
SYNCSE B2 I JESD204B SYNC signal single-ended active low input. This pin provides the JESD204B-required synchronization request input. A logic low applied to this input initiates code group synchronization and the initial lane alignment sequence. The choice of single-ended or differential SYNC (using TMSTP+ and TMSTP- pins) is selected by programming SYNC_SEL. This pin should be tied to GND if differential SYNC (TMSTP±) is used as the JESD204B SYNC signal.
SYSREF+ L1 I SYSREF positive input used to achieve synchronization and deterministic latency across the JESD204B interface. This differential input (SYSREF+ to SYSREF–) has an internal 100-Ω differential termination. It is self-biased when AC coupled (SYSREF_LVPECL_EN must be set to 0), but can be DC coupled by setting SYSREF_LVPECL_EN to 1, which changes the internal termination to 50-Ω single-ended termination to ground on each SYSREF+ and SYSREF- input. The common mode voltage must be within the recommended range when DC coupled.
SYSREF– M1 I SYSREF negative input.
TDIODE+ N2 I Temperature diode positive (anode) connection. An external temperature sensor can be connected to TDIODE+ and TDIODE– to monitor the junction temperature of the device. This pin can be left disconnected if not used.
TDIODE– P2 I Temperature diode negative (cathode) connection. This pin can be left disconnected if not used.
TMSTP+ C1 I Timestamp input positive connection or differential JESD204B SYNC positive connection. This input is used as the timestamp input when SYNC_SEL is set to use SYNCSE as the JESD204B SYNC signal. This input is used as the JESD204B SYNC signal when SYNC_SEL is set to use TMSTP+ and TMSTP– as the JESD204B SYNC signal. For additional usage information as timestamp input, see the Timestamp section. This pin can be left disconnected if SYNCSE is used and timestamp is not required.
TMSTP– D1 I Timestamp input positive connection or differential JESD204B SYNC negative connection. This pin can be left disconnected if SYNCSE is used and timestamp is not required.
VA11 D3, E3, F2, F3, G3, H3, J2, J3, K3, L3 I 1.1-V analog supply.
VA19 C2, C3, C4, C5, D2, E1, E2, K1, K2, L2, M2, M3, M4, M5 I 1.9-V analog supply.
VD11 C10, C11, C12, D12, E12, F12, G12, H12, J12, K12, L12, M10, M11, M12 I 1.1-V digital supply.