SLVSDR3C may   2018  – may 2023 ADC12DL3200

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Revision History
  6. 5Pin Configuration and Functions
  7. 6Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: DC Specifications
    6. 6.6  Electrical Characteristics: Power Consumption
    7. 6.7  Electrical Characteristics: AC Specifications (Dual-Channel Mode)
    8. 6.8  Electrical Characteristics: AC Specifications (Single-Channel Mode)
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Typical Characteristics
  8. 7Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
        1. 7.3.1.1 Analog Input Protection
        2. 7.3.1.2 Full-Scale Voltage (VFS) Adjustment
        3. 7.3.1.3 Analog Input Offset Adjust
      2. 7.3.2 ADC Core
        1. 7.3.2.1 ADC Theory of Operation
        2. 7.3.2.2 ADC Core Calibration
        3. 7.3.2.3 ADC Overrange Detection
        4. 7.3.2.4 Code Error Rate (CER)
        5. 7.3.2.5 Internal Dither
      3. 7.3.3 Timestamp
      4. 7.3.4 Clocking
        1. 7.3.4.1 Noiseless Aperture Delay Adjustment (tAD Adjust)
        2. 7.3.4.2 Aperture Delay Ramp Control (TAD_RAMP)
        3. 7.3.4.3 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          1. 7.3.4.3.1 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
          2. 7.3.4.3.2 Automatic SYSREF Calibration
      5. 7.3.5 LVDS Digital Interface
        1. 7.3.5.1 Multi-Device Synchronization and Deterministic Latency Using Strobes
          1. 7.3.5.1.1 Dedicated Strobe Pins
          2. 7.3.5.1.2 Reduced Width Interface With Dedicated Strobe Pins
          3. 7.3.5.1.3 LSB Replacement With a Strobe
          4. 7.3.5.1.4 Strobe Over All Data Pairs
      6. 7.3.6 Alarm Monitoring
        1. 7.3.6.1 Clock Upset Detection
      7. 7.3.7 Temperature Monitoring Diode
      8. 7.3.8 Analog Reference Voltage
    4. 7.4 Device Functional Modes
      1. 7.4.1 Dual-Channel Mode (Non-DES Mode)
      2. 7.4.2 Internal Dither Modes
      3. 7.4.3 Single-Channel Mode (DES Mode)
      4. 7.4.4 LVDS Output Driver Modes
      5. 7.4.5 LVDS Output Modes
        1. 7.4.5.1 Staggered Output Mode
        2. 7.4.5.2 Aligned Output Mode
        3. 7.4.5.3 Reducing the Number of Strobes
        4. 7.4.5.4 Reducing the Number of Data Clocks
        5. 7.4.5.5 Scrambling
        6. 7.4.5.6 Digital Interface Test Patterns and LVSD SYNC Functionality
          1. 7.4.5.6.1 Active Pattern
          2. 7.4.5.6.2 Synchronization Pattern
          3. 7.4.5.6.3 User-Defined Test Pattern
      6. 7.4.6 Power-Down Modes
      7. 7.4.7 Calibration Modes and Trimming
        1. 7.4.7.1 Foreground Calibration Mode
        2. 7.4.7.2 Background Calibration Mode
        3. 7.4.7.3 Low-Power Background Calibration (LPBG) Mode
      8. 7.4.8 Offset Calibration
      9. 7.4.9 Trimming
    5. 7.5 Programming
      1. 7.5.1 Using the Serial Interface
        1. 7.5.1.1 SCS
        2. 7.5.1.2 SCLK
        3. 7.5.1.3 SDI
        4. 7.5.1.4 SDO
        5. 7.5.1.5 78
        6. 7.5.1.6 Streaming Mode
        7. 7.5.1.7 80
    6. 7.6 Register Maps
      1. 7.6.1 SPI_REGISTER_MAP Registers
  9.   Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Wideband RF Sampling Receiver
        1. 8.2.1.1 Design Requirements
          1. 8.2.1.1.1 Input Signal Path
          2. 8.2.1.1.2 Clocking
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Calculating Values of AC-Coupling Capacitors
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Reconfigurable Dual-Channel, 2.5-GSPS or Single-Channel, 5.0-GSPS Oscilloscope
        1. 8.2.2.1 Design Requirements
          1. 8.2.2.1.1 Input Signal Path
          2. 8.2.2.1.2 Clocking
          3. 8.2.2.1.3 The ADC12DL3200
        2. 8.2.2.2 Application Curves
    3. 8.3 Initialization Set Up
    4. 8.4 Power Supply Recommendations
      1. 8.4.1 Power Sequencing
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 8Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  11. 9Mechanical, Packaging, and Orderable Information

6.10 Switching Characteristics

typical values at TA = +25°C, nominal supply voltages, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000), fIN = 248 MHz, AIN = –1 dBFS, fCLK = maximum rated clock frequency, filtered 1-VPP-DIFF sine-wave clock, DES_EN = 1, LDEMUX = 1, LALIGNED = 0, ADC_DITH = 0x01, LVDS driver high-swing mode (HSM), background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over operating free-air temperature range provided in the Recommended Operating Conditions table
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
DEVICE (SAMPLING) CLOCK (CLK+, CLK–)
tADSampling (aperture) delay from CLK± rising edge (dual channel mode) or rising and falling edge (single channel mode) to sampling instant(4)TAD_COARSE = 0x00, TAD_FINE = 0x00 and TAD_INV = 0360ps
tAD(MAX)Maximum tAD Adjust programmable delay, not including clock inversion (TAD_INV = 0)Coarse adjustment (TAD_COARSE = 0xFF)289ps
Fine adjustment (TAD_FINE = 0xFF)4.9
tAD(STEP)Aperture delay step sizeCoarse adjustment (TAD_COARSE)1.13ps
Fine adjustment (TAD_FINE)19fs
tAJAperture jitter, rmsMinimum tAD Adjust coarse setting (TAD_COARSE = 0x00, TAD_INV = 0), dither disabled (ADC_DITH_EN = 0)55fs
Minimum tAD Adjust coarse setting (TAD_COARSE = 0xFF, TAD_INV = 0), dither enabled (ADC_DITH_EN = 1)70
Maximum tAD Adjust coarse setting (TAD_COARSE = 0xFF) excluding TAD_INV (TAD_INV = 0), dither disabled (ADC_DITH_EN = 0)70(1)
Maximum tAD Adjust coarse setting (TAD_COARSE = 0xFF) excluding TAD_INV (TAD_INV = 0), dither enabled (ADC_DITH_EN = 1)80(1)
LVDS OUTPUTS (DACLK±, DASTR±, DA[11:0]±, DBCLK±, DBSTR±, DB[11:0]±, DCCLK±, DCSTR±, DC[11:0]±, DDCLK±, DDSTR±, DD[11:0]±)
fBITOutput bit rate per output data pair1.6Gbps
fDCLKDDR data clock frequency800MHz
tDJDDR data clock total jitter, peak-to-peak, with random jitter portion defined with respect to a BER=1e–15 (Q=7.94)UPAT_CTRL = 0x1036ps
tSKEW(SAME)Maximum timing skew between any two LVDS output pairs (DxCLK±, Dx[11:0]±, DxSTR±) within the same LVDS bank over operating conditions75ps
tSKEW(ALL)Maximum timing skew between any two LVDS output pairs (DxCLK±, Dx[11:0]±, DxSTR±) in all LVDS banks over operating conditions with tOSAB, tOSAC and tOSBD skew excluded125ps
tOSABFunctional timing offset between DACLK± rising edge and DBCLK± rising edge, positive number indicates that DACLK± leads DBCLK±DES_EN = 0, LDEMUX = 0, LALIGNED = 00tCLK
DES_EN = 0, LDEMUX = 0, LALIGNED = 10
DES_EN = 0, LDEMUX = 1, LALIGNED = 00
DES_EN = 0, LDEMUX = 1, LALIGNED = 10
DES_EN = 1, LDEMUX = 0, LALIGNED = 00.5
DES_EN = 1, LDEMUX = 0, LALIGNED = 10
DES_EN = 1, LDEMUX = 1, LALIGNED = 00.5
DES_EN = 1, LDEMUX = 1, LALIGNED = 10
tOSACFunctional timing offset between DACLK± rising edge and DCCLK± rising edge, positive number indicates that DACLK± leads DCCLK±DES_EN = 0, LDEMUX = 1, LALIGNED = 01tCLK
DES_EN = 0, LDEMUX = 1, LALIGNED = 10
DES_EN = 1, LDEMUX = 1, LALIGNED = 01
DES_EN = 1, LDEMUX = 1, LALIGNED = 10
tOSBDFunctional timing offset between DBCLK± rising edge and DDCLK± rising edge, positive number indicates that DBCLK± leads DDCLK±DES_EN = 0, LDEMUX = 1, LALIGNED = 01tCLK
DES_EN = 0, LDEMUX = 1, LALIGNED = 10
DES_EN = 1, LDEMUX = 1, LALIGNED = 01
DES_EN = 1, LDEMUX = 1, LALIGNED = 10
tTLHLow-to-high transition time (differential)20% to 80%, 1.6 Gbps, VLVDS = 1.9 V, UPAT_CTRL = 0x10125ps
20% to 80%, 1.6 Gbps, VLVDS = 1.1 V, UPAT_CTRL = 0x10200
tTHLHigh-to-low transition time (differential)80% to 20%, 1.6 Gbps, VLVDS = 1.9 V, UPAT_CTRL = 0x10125ps
80% to 20%, 1.6 Gbps, VLVDS = 1.1 V, UPAT_CTRL = 0x10200
LATENCY
tODOutput delay from CLK± rising edge (dual-channel mode) or falling edge (single-channel mode) to DACLK± output(4)TAD_COARSE = 0x00, TAD_FINE = 0x00 and TAD_INV = 01.5ns
tLAT(DIG)CLK± edge that samples input signal to CLK± edge that launches data, digital latency only(2)(4)DES_EN = 0, LDEMUX = 0, LALIGNED = 026tCLK
DES_EN = 0, LDEMUX = 0, LALIGNED = 126
DES_EN = 0, LDEMUX = 1, LALIGNED = 026
DES_EN = 0, LDEMUX = 1, LALIGNED = 127
DES_EN = 1, LDEMUX = 0, LALIGNED = 026
DES_EN = 1, LDEMUX = 0, LALIGNED = 126.5
DES_EN = 1, LDEMUX = 1, LALIGNED = 026
DES_EN = 1, LDEMUX = 1, LALIGNED = 127.5
tLAT(STB)Latency from SYSREF± being sampled by rising edge of CLK± to the start of the corresponding data frame(3)DES_EN = 0, LDEMUX = 0, LALIGNED = 047tCLK
DES_EN = 0, LDEMUX = 0, LALIGNED = 147
DES_EN = 0, LDEMUX = 1, LALIGNED = 047
DES_EN = 0, LDEMUX = 1, LALIGNED = 148
DES_EN = 1, LDEMUX = 0, LALIGNED = 046.5
DES_EN = 1, LDEMUX = 0, LALIGNED = 147
DES_EN = 1, LDEMUX = 1, LALIGNED = 046.5
DES_EN = 1, LDEMUX = 1, LALIGNED = 148
tLAT( SYNCSE)Latency from SYNCSE assertion or deassertion to DB0± (LSB) changing from normal data to strobe output or strobe output to normal data, digital latency onlyLDEMUX = 02636+1*LFRAMEtCLK
LDEMUX = 12636+2*LFRAME
SERIAL PROGRAMMING INTERFACE (SDO)
t(OZD)Delay from falling edge of 16th SCLK cycle during read operation for SDO transition from tri-state to valid data1ns
t(ODZ)Delay from SCS rising edge for SDO to transition from valid data to tri-state10ns
t(OD)Delay from falling edge of SCLK during read operation to SDO valid110ns
(1) tAJ increases because of additional attenuation on internal clock path.
(2) When LDEMUX = 1 the output buses are aligned in time requiring the earlier sample(s) to be delayed before outputting on the LVDS buses to align with the later samples. The latency for the buses will be slightly different due to added delays. The number shown is for the worst case bus.
(3) When LDEMUX = 0 the output buses are staggered in time and therefore the start of data frames occur at staggered times. The number shown is for the earliest output frame. The strobe signals are output at the end of a frame so the start of a data frame corresponds to the data output immediately after a strobe output.
(4) Both tAD and tOD increase by the delay introduced by TAD_COARSE, TAD_FINE and TAD_INV when tAD Adjust is used to delay the sampling instant. The total latency through the device does not include the aperture delay. Total latency through device is tLAT = tLAT(DIG) + tOD - tAD.
GUID-2599E9DF-DDC4-4D8D-88C1-236AF7C833DD-low.gif
tSU(SYSREF) and tH(SYSREF) are only shown for completeness. Use automatic SYSREF calibration or SYSREF windowing to meet SYSREF timing.
Figure 6-1 Dual-Channel, 2-Bus Mode Timing (LDEMUX = 0, DES_EN = 0, LALIGNED = 0 or 1)
GUID-04016000-EA7B-4D4A-8882-91E7F8D4F5C2-low.gif
tSU(SYSREF) and tH(SYSREF) are only shown for completeness. Use automatic SYSREF calibration or SYSREF windowing to meet SYSREF timing.
Figure 6-2 Dual-Channel, 4-Bus, Staggered-Mode Timing (LDEMUX = 1, DES_EN = 0, LALIGNED = 0)
GUID-B0AEBEC0-47EF-46E3-A6E1-893AED43DAA0-low.gif
tSU(SYSREF) and tH(SYSREF) are only shown for completeness. Use automatic SYSREF calibration or SYSREF windowing to meet SYSREF timing.
Figure 6-3 Dual-Channel, 4-Bus, Aligned-Mode Timing (LDEMUX = 1, DES_EN = 0, LALIGNED = 1)
GUID-023FF6C1-0189-4835-A248-9C17939E6ED7-low.gif
tSU(SYSREF) and tH(SYSREF) are only shown for completeness. Use automatic SYSREF calibration or SYSREF windowing to meet SYSREF timing.
Figure 6-4 Single-Channel, 2-Bus, Staggered-Mode Timing (LDEMUX = 0, DES_EN = 1, LALIGNED = 0)
GUID-70843E92-CFF4-4689-BAB7-03944875898F-low.gif
tSU(SYSREF) and tH(SYSREF) are only shown for completeness. Use automatic SYSREF calibration or SYSREF windowing to meet SYSREF timing.
Figure 6-5 Single-Channel, 2-Bus, Aligned-Mode Timing (LDEMUX = 0, DES_EN = 1, LALIGNED = 1)
GUID-32153316-F28C-4C4B-902B-11E7145F7A49-low.gif
tSU(SYSREF) and tH(SYSREF) are only shown for completeness. Use automatic SYSREF calibration or SYSREF windowing to meet SYSREF timing.
Figure 6-6 Single-Channel, 4-Bus, Staggered-Mode Timing (LDEMUX = 1, DES_EN = 1, LALIGNED = 0)
GUID-E938B527-74EF-485B-B5BC-F1E5EAB753DB-low.gif
tSU(SYSREF) and tH(SYSREF) are only shown for completeness. Use automatic SYSREF calibration or SYSREF windowing to meet SYSREF timing.
Figure 6-7 Single-Channel, 4-Bus, Aligned-Mode Timing (LDEMUX = 1, DES_EN = 1, LALIGNED = 1)
GUID-D45CA475-67B8-492C-929E-45CB1AC7584C-low.gifFigure 6-8 SYNCSE Timing Diagram
GUID-DE994376-13A5-439C-B57E-FD75F5375847-low.gifFigure 6-9 Serial Interface Timing