SLVSE40C February 2018 – September 2019 BQ25882
PRODUCTION DATA.
REG07 is shown in Figure 44 and described in Table 16.
Return to Summary Table.
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reset | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
Field | PFM_DIS | WD_RST | TOPOFF_TIMER[1:0] | SYS_MIN[3:0] |
Bit | Field | Type | Reset by REG_RST | Reset by WATCHDOG | Description | |
---|---|---|---|---|---|---|
7 | PFM_DIS | R/W | Yes | No | PFM Mode Disable control:
0 – Enable PFM operation (default) 1 – Disable PFM operation |
|
6 | WD_RST | R/W | Yes | Yes | I2C Watchdog Timer Reset:
0 – Normal 1 – Reset (Bit goes back to 0 after timer reset) |
|
5 | TOPOFF_TIMER[1] | R/W | Yes | Yes | Top-off Timer Control :
00 – Disabled (default) 01 – 15 mins 10 – 30 mins 11 – 45 mins |
|
4 | TOPOFF_TIMER[0] | R/W | Yes | Yes | ||
3 | SYS_MIN[3] | R/W | Yes | No | 800 mV | Minimum System Voltage Limit
Offset: 6.0 V Range: 6.0 V – 7.5 V Default: 7.0 V |
2 | SYS_MIN[2] | R/W | Yes | No | 400 mV | |
1 | SYS_MIN[2] | R/W | Yes | No | 200 mV | |
0 | SYS_MIN[0] | R/W | Yes | No | 100 mV |