SLVSE46A November 2017 – January 2018 TPS65680
PRODUCTION DATA.
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
CS1 | 21 | ANALOG | Charge sharing / gate voltage shaping pin for GCK1, 2, 3, 4, 5, 6. Leave floating if not used. |
CS2 | 20 | ANALOG | Charge sharing / gate voltage shaping pin for GCK7, 8, 9, 10, 11, 12. Leave floating if not used. |
GCK1 | 27 | O | Analog, high-voltage clock output with charge sharing / gate voltage shaping connected to CS1. Outputs default to VGL2 and should left floating if not used. |
GCK2 | 26 | O | |
GCK3 | 25 | O | |
GCK4 | 24 | O | |
GCK5 | 23 | O | Analog, high-voltage clock output with charge sharing / gate voltage shaping connected to CS1. Outputs default to VGL2 and should left floating if not used. |
GCK6 | 22 | O | |
GCK7 | 19 | O | Analog, high-voltage clock output with charge sharing / gate voltage shaping connected to CS2. Outputs default to VGL1 and should left floating if not used. |
GCK8 | 18 | O | |
GCK9 | 17 | O | Analog, high-voltage clock output with charge sharing / gate voltage shaping connected to CS2. Outputs default to VGL2 and should left floating if not used. |
GCK10 | 16 | O | |
GCK11 | 15 | O | |
GCK12 | 14 | O | |
GCP | 13 | O | Analog, high-voltage gate-clear-pulse output. Outputs default to VGL2 and should left floating if not used. |
GGP1 | 11 | O | Analog, high-voltage general-purpose output. Outputs default to VGL2 and should left floating if not used. |
GGP2 | 10 | O | |
GND | 31 | GND | Ground. |
GSP1 | 29 | O | Analog, high-voltage gate-start-pulse output. Outputs default to VGL2 and should left floating if not used. |
GSP2 | 28 | O | |
I2CSEL | 6 | I | I2C slave address selection pin. |
LN_CLK | 3 | I | PLL input clock (line-clock from TCON). |
LS_CNTRL | 4 | I | Enable and panel discharge pin. Enables toggling of level shifter outputs when pulled high and initiates panel discharge sequence when pulled low. |
LS_START | 5 | I | Pattern start. Pattern address pointer is reset to start address when pulled high. See functional description for details. |
OTP_LDO | 7 | POWER | OTP LDO regulator output pin. Connect directly to filter capacitor. |
PLLC | 32 | I | PLL loop filter input. Connect directly to filter capacitor. |
SCL | 1 | I | I2C interface clock line. |
SDA | 2 | I/O | I2C interface data line. |
VGH | 30 | POWER | VGH supply pin. |
VGL1 | 9 | POWER | Negative input supply pin for GCK7 and GCK8 outputs. |
VGL2 | Pad | POWER | Connect the thermal pad to the most negative supply (VGL2). If no second negative supply is used, connect to VGL1. Do not tie thermal pad to GND. |
VIN | 8 | POWER | Supply pin for digital core. |
VSS | 12 | O | Analog, high-voltage panel discharge output signal / low-side supply connected to VGL2. |