SLVSE46A November 2017 – January 2018 TPS65680
PRODUCTION DATA.
To stay in sync with the source driver data, a reference clock must be provided to the level shifter. This reference clock is typically the line clock, provided by the timing controller. The pattern sequencer, however, needs to run at a higher frequency to provide enough timing resolution to time the charge sharing or gate voltage shaping period, which is typically a fraction of the line time. This higher frequency is generated by the internal PLL. The PLL output frequency equals the input clock (LN_CLK) times the multiplication factor (MPL[2:0]). The multiplication factor is set by the MPL[2:0] bits of the register and recommended settings are shown below.
DISPLAY LINE COUNT | REFRESH RATE [Hz] | LINE FREQUENCY [kHz] | LINE TIME [µs] | PLL MULTIPLIER | PLL OUTPUT FREQUENCY [MHz] | TIMING RESOLUTION [ns] |
---|---|---|---|---|---|---|
720 | 60 | 43.2 | 23.1 | 160 | 6.9 | 144 |
768 | 60 | 46.1 | 21.7 | 7.4 | 135 | |
800 | 60 | 48.0 | 20.8 | 7.7 | 130 | |
1050 | 60 | 63.0 | 15.9 | 128 | 8.1 | 124 |
1080 | 60 | 64.8 | 15.4 | 8.3 | 120 | |
1200 | 60 | 72.0 | 13.9 | 9.2 | 108 | |
1440 | 60 | 86.4 | 11.6 | 96 | 8.3 | 120 |
1600 | 60 | 96.0 | 10.4 | 9.2 | 108 | |
2160 | 60 | 129.6 | 7.7 | 64 | 8.3 | 120 |
720 | 120 | 86.4 | 11.6 | 80 | 6.9 | 144 |
768 | 120 | 92.2 | 10.9 | 7.4 | 135 | |
800 | 120 | 96.0 | 10.4 | 7.7 | 130 | |
1050 | 120 | 126 | 7.9 | 64 | 8.1 | 124 |
1080 | 120 | 129.6 | 7.7 | 8.3 | 120 | |
1200 | 120 | 144.0 | 6.9 | 9.2 | 108 | |
1440 | 120 | 172.8 | 5.8 | 48 | 8.3 | 120 |
1600 | 120 | 192.0 | 5.2 | 9.2 | 108 | |
2160 | 120 | 259.2 | 3.9 | 32 | 8.3 | 120 |