SLVSEA2D
August 2020 – April 2024
DRV8714-Q1
,
DRV8718-Q1
PRODMIX
1
1
Features
2
Applications
3
Description
4
Device Comparison Table
5
Pin Configuration and Functions
5.1
VQFN (RVJ) 56-Pin Package and Pin Functions
5.2
VQFN (RHA) 40-Pin Package and Pin Functions
5.3
HTQFP (PHP) 48-Pin Package and Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Timing Requirements
6.7
Timing Diagrams
6.8
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
External Components
7.3.2
Device Interface Variants
7.3.2.1
Serial Peripheral Interface (SPI)
7.3.2.2
Hardware (H/W)
7.3.3
Input PWM Control Modes
7.3.3.1
Half-Bridge Control Scheme With Input PWM Mapping
7.3.3.1.1
DRV8718-Q1 Half-Bridge Control
7.3.3.1.2
DRV8714-Q1 Half-Bridge Control
7.3.3.2
H-Bridge Control
7.3.3.2.1
DRV8714-Q1 H-Bridge Control
7.3.3.3
Split HS and LS Solenoid Control
7.3.3.3.1
DRV8714-Q1 Split HS and LS Solenoid Control
7.3.4
Smart Gate Driver
7.3.4.1
Functional Block Diagram
7.3.4.2
Slew Rate Control (IDRIVE)
7.3.4.3
Gate Drive State Machine (TDRIVE)
7.3.4.4
Propagation Delay Reduction (PDR)
7.3.4.4.1
PDR Pre-Charge/Pre-Discharge Control Loop Operation Details
7.3.4.4.1.1
PDR Pre-Charge/Pre-Discharge Setup
7.3.4.4.2
PDR Post-Charge/Post-Discharge Control Loop Operation Details
7.3.4.4.2.1
PDR Post-Charge/Post-Discharge Setup
7.3.4.4.3
Detecting Drive and Freewheel MOSFET
7.3.4.5
Automatic Duty Cycle Compensation (DCC)
7.3.4.6
Closed Loop Slew Time Control (STC)
7.3.4.6.1
STC Control Loop Setup
7.3.5
Tripler (Dual-Stage) Charge Pump
7.3.6
Wide Common-Mode Current Shunt Amplifiers
7.3.7
Pin Diagrams
7.3.7.1
Logic Level Input Pin (INx/ENx, INx/PHx, nSLEEP, nSCS, SCLK, SDI)
7.3.7.2
Logic Level Push Pull Output (SDO)
7.3.7.3
Logic Level Multi-Function Pin (DRVOFF/nFLT)
7.3.7.4
Quad-Level Input (GAIN, MODE)
7.3.7.5
Six-Level Input (IDRIVE, VDS)
7.3.8
Protection and Diagnostics
7.3.8.1
Gate Driver Disable (DRVOFF/nFLT and EN_DRV)
7.3.8.2
Low IQ Powered Off Braking (POB, BRAKE)
7.3.8.3
Fault Reset (CLR_FLT)
7.3.8.4
DVDD Logic Supply Power on Reset (DVDD_POR)
7.3.8.5
PVDD Supply Undervoltage Monitor (PVDD_UV)
7.3.8.6
PVDD Supply Overvoltage Monitor (PVDD_OV)
7.3.8.7
VCP Charge Pump Undervoltage Lockout (VCP_UV)
7.3.8.8
MOSFET VDS Overcurrent Protection (VDS_OCP)
7.3.8.9
Gate Driver Fault (VGS_GDF)
7.3.8.10
Thermal Warning (OTW)
7.3.8.11
Thermal Shutdown (OTSD)
7.3.8.12
Offline Short Circuit and Open Load Detection (OOL and OSC)
7.3.8.13
Watchdog Timer
7.3.8.14
Fault Detection and Response Summary Table
7.4
Device Functional Modes
7.4.1
Inactive or Sleep State
7.4.2
Standby State
7.4.3
Operating State
7.5
Programming
7.5.1
SPI Interface
7.5.2
SPI Format
7.5.3
SPI Interface for Multiple Slaves
7.5.3.1
SPI Interface for Multiple Slaves in Daisy Chain
8
Register Maps
8.1
DRV8718-Q1 Register Map
8.2
DRV8714-Q1 Register Map
8.3
DRV8718-Q1 Register Descriptions
8.3.1
DRV8718-Q1_STATUS Registers
8.3.2
DRV8718-Q1_CONTROL Registers
8.3.3
DRV8718-Q1_CONTROL_ADV Registers
8.3.4
DRV8718-Q1_STATUS_ADV Registers
8.4
DRV8714-Q1 Register Descriptions
8.4.1
DRV8714-Q1_STATUS Registers
8.4.2
DRV8714-Q1_CONTROL Registers
8.4.3
DRV8714-Q1_CONTROL_ADV Registers
8.4.4
DRV8714-Q1_STATUS_ADV Registers
9
Application Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
Gate Driver Configuration
9.2.2.1.1
VCP Load Calculation Example
9.2.2.1.2
IDRIVE Calculation Example
9.2.2.1.3
tDRIVE Calculation Example
9.2.2.1.4
Maximum PWM Switching Frequency
9.2.2.2
Current Shunt Amplifier Configuration
9.2.2.3
Power Dissipation
9.2.3
Application Curves
9.3
Initialization
9.4
Power Supply Recommendations
9.4.1
Bulk Capacitance Sizing
9.5
Layout
9.5.1
Layout Guidelines
9.5.2
Layout Example
10
Device Documentation and Support
10.1
Documentation Support
10.1.1
Related Documents
10.2
Receiving Notification of Documentation Updates
10.3
Support Resources
10.4
Trademarks
10.5
Electrostatic Discharge Caution
10.6
Glossary
11
Revision History
12
Mechanical, Packaging, and Orderable Information
12.1
Package Option Addendum
1
Features
AEC-Q100 qualified for automotive applications:
Temperature grade 1: –40°C to +125°C, T
A
Multi-channel half-bridge gate drivers
Pin to pin 4 and 8 half-bridge driver variants
4.9V to 37V (40V abs. max) operating range
4 PWM inputs with output mapping
Tripler charge pump for 100% PWM
Half-bridge, H-bridge, and SPI control modes
Smart multi-stage gate drive architecture
Adjustable slew rate control
Adaptive propagation delay control
50µA to 62mA peak source current output
50µA to 62mA peak sink current output
Integrated dead-time handshaking
2x wide common mode current shunt amplifiers
Supports inline, high-side, or low-side
Adjustable gain settings (10, 20, 40, 80V/V)
Multiple interface options available
SPI: Detailed configuration and diagnostics
H/W: Simplified control and less MCU pins
Compact VQFN packages with wettable flanks
Integrated protection features
Dedicated driver disable pin (DRVOFF)
Low I
Q
, sleep mode motor braking (BRAKE)
Supply and regulator voltage monitors
MOSFET V
DS
overcurrent monitors
MOSFET V
GS
gate fault monitors
Charge pump for reverse polarity MOSFET
Offline open load and short circuit diagnostics
Device thermal warning and shutdown
Window watchdog timer
Fault condition interrupt pin (nFAULT)