SLVSEI1C June 2019 – October 2020 TPS62864 , TPS62866
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
SUPPLY | ||||||
IQ | Quiescent current | EN = High, no load, device not switching | 4 | 10 | µA | |
ISD | Shutdown current | EN = Low, TJ = -40℃ to 85℃ |
0.1 | 1 | µA | |
VUVLO | Under voltage lock out threshold | VIN rising | 2.2 | 2.3 | 2.4 | V |
VIN falling | 2.1 | 2.2 | 2.3 | V | ||
TJW | Thermal warning threshold | TJ rising | 130 | °C | ||
Thermal warning hysteresis | TJ falling | 20 | °C | |||
TJSD | Thermal shutdown threshold | TJ rising | 150 | °C | ||
Thermal shutdown hysteresis | TJ falling | 20 | °C | |||
LOGIC INTERFACE EN, SDA, SCL | ||||||
VIH | High-level input threshold voltage at EN, SCL, SDA, VSET/VID | 1.0 | V | |||
VIL | Low-level input threshold voltage at EN, SCL, SDA, VSET/VID | 0.4 | V | |||
ISCL,LKG | Input leakage current into SCL pin | 0.01 | 0.2 | µA | ||
ISDA,LKG | Input leakage current into SDA pin | 0.01 | 0.1 | µA | ||
IEN,LKG | Input leakage current into EN pin | 0.01 | 0.1 | µA | ||
CSCL | Parasitic capacitance at SCL | 1 | pF | |||
CSDA | Parasitic capacitance at SCL | 2.4 | pF | |||
STARTUP, POWER GOOD | ||||||
tDelay | Enable delay time | Time from EN high to device starts switching, R1 = 249kΩ | 420 | 700 | 1100 | µs |
tRamp | Output voltage ramp time | Time from device starts switching to power good | 0.9 | 1 | 1.5 | ms |
VPG | Power good lower threshold | VVOS referenced to VOUT nominal | 85 | 91 | 96 | % |
Power good upper threshold | VVOS referenced to VOUT nominal | 103 | 111 | 120 | % | |
tPG,DLY | Power good deglitch delay | Rising and falling edges | 34 | µs | ||
OUTPUT | ||||||
VOUT | Output voltage accuracy(1) | VOUT ≥ 0.59 V, FPWM, no Load, TJ = 25℃ to 125℃ | -1 | 1 | % | |
VOUT < 0.59 V, FPWM, no Load, TJ = 25℃ to 125℃ | -2 | 2 | % | |||
IVOS,LKG | Input leakage current into VOS pin | EN = High, VVOS = 1.8 V | 18 | µA | ||
EN = Low, Output discharge disabled, VVOS = 1.8 V | 0.2 | 2.5 | µA | |||
RDIS | Output discharge resistor at VOS pin | 15 | Ω | |||
Load regulation | VOUT = 0.9 V, FPWM | 0.04 | %/A | |||
POWER SWITCH | ||||||
RDS(on) | High-side FET on-resistance | 7 | mΩ | |||
Low-side FET on-resistance | 6.5 | mΩ | ||||
ILIM | High-side FET forward current limit | TPS62864 | 5 | 5.5 | 6 | A |
TPS62866 | 7 | 7.7 | 8.5 | A | ||
Low-side FET forward current limit | TPS62864 | 4.5 | A | |||
TPS62866 | 6.5 | A | ||||
Low-side FET negative current limit | TPS62864, TPS62866 | -3 | A | |||
fSW | PWM switching frequency | IOUT = 1 A, VOUT = 0.9 V | 2.4 | MHz |